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[SPIR-V][vk::SampledTexture] #5. Add remaining .Sample...() methods for vk::SampledTexture2D` type.#8098

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luciechoi wants to merge 14 commits intomicrosoft:mainfrom
luciechoi:samplebias
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[SPIR-V][vk::SampledTexture] #5. Add remaining .Sample...() methods for vk::SampledTexture2D` type.#8098
luciechoi wants to merge 14 commits intomicrosoft:mainfrom
luciechoi:samplebias

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@luciechoi luciechoi commented Jan 26, 2026

Part of #7979

Implement remaining sample methods methods for vk::SampledTexture2D:

float Object.SampleCmp(float Location, float CompareValue, [, int Offset], [, float Clamp] [, out uint Status]);
float Object.SampleCmpLevelZero(float Location, float CompareValue, [, int Offset], [, out uint Status]);
float Object.SampleCmpLevel(float Location, float CompareValue, float LOD, [, int Offset], [, out uint Status]);
float Object.SampleGrad(float Location, float DDX, float DDY, [, int Offset], [, float Clamp] [, out uint Status]);
float Object.SampleCompGrad(float Location, float CompareValue, float DDX, float DDY, [, int Offset], [, float Clamp] [, out uint Status]);
float Object.SampleCompBias(float Location, float CompareValue, float Bias, [, int Offset], [, float Clamp] [, out uint Status]);
PARAM_TYPE Object.SampleBias(float Location, float Bias, [, int Offset], [, float Clamp], [, out uint Status]);
PARAM_TYPE Object.SampleLevel(float Location, float LOD, [, int Offset], [, out uint Status]);

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/azp run

@s-perron s-perron enabled auto-merge (squash) February 11, 2026 16:37
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@s-perron s-perron disabled auto-merge February 11, 2026 16:37
@luciechoi luciechoi changed the title [SPIR-V] Implement remaining .Sample... methods for vk::SampledTexture2D type. [SPIR-V][vk::SampledTexture] #5. Add remaining .Sample...() methods for vk::SampledTexture2D` type. Feb 17, 2026
@luciechoi luciechoi force-pushed the samplebias branch 3 times, most recently from eb06b32 to 2206f52 Compare February 17, 2026 19:15
Implement `GetDimensions` based on new method.
Implement  using new method
SampleCmpLevel, SampleCmpGrad, SampleCmpBias
Comment on lines 6009 to 6014
if (numArgs > offsetIndex &&
expr->getArg(offsetIndex)->getType()->isFloatingType())
clamp = doExpr(expr->getArg(offsetIndex));
else if (numArgs > offsetIndex + 1 &&
expr->getArg(offsetIndex + 1)->getType()->isFloatingType())
clamp = doExpr(expr->getArg(offsetIndex + 1));
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I find it confusing to load the clamp value from the offsetIndex. Why is that and not the clampIndex?

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Thanks for pointing out, I agree it's confusing. There was a discussion around deriving the index from non-optional argument indices. But offset here is also optional, so it's incorrect.

In fact, I noticed there was a helper method to handle these common cases, so refactored. PTAL!

luciechoi and others added 8 commits February 19, 2026 21:24
…icrosoft#8170)

Test uses `-spirv` but lacks the `REQUIRES: spirv` annotation, so it
runs and fails under `-DENABLE_SPIRV_CODEGEN=OFF`.

---------

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
microsoft/hlsl-specs#783 changed the names of
the linalg DXIL ops, update the implementation to reflect that.

The only interesting changes are in `utils/hct/hctdb.py` and
`lib/HLSL/HLOperationLower.cpp` everything else is generated code
…ateDxilComputeAndNodeCommonInputs() (microsoft#8022)

As a result of
microsoft#7799, the HLSL
entry function can now contain `dbg.value` calls with !dbg location
metadata with scopes corresponding to functions which have been inlined.
The `HLSignatureLower::GenerateDxilComputeAndNodeCommonInputs()` creates
`@dx.op.threadId` intrinsic calls, using the default dbg loc when
creating an `IRBuilder`. When the first instruction in the entry block
is one of the `dbg,value` calls, its dbg location is copied to the
`@dx.op.threadId` calls. That makes the DXIL unreadable by the modern
LLVM IR reader since it fails the IR module verification because of !dbg
pointing to a different subprogram scope.

This change sets the dbg location for IRBuilder to be the !dbg node of
the first non-PHI and non-debug instruction in the block.

---------

Co-authored-by: Konstantin <konstantin.pyzhov@amd.com>
…t#8167)

We are updating the spir-v submodules. They contain a new pass that will
linearize multi-dimensional resource arrays, and call the combine access
chain pass.

This means we need to fix up some tests, and we want to make sure that
we can properly handle multi-dimensional resource array in DXC.

Fixes microsoft#7922
Resolves the `int MatrixRef` TODO left from previous changes, as well as
updates most builtins to match their final shape.

This should be considered an NFC change since these builtins aren't
implemented yet and instead we are just updating the shape of the
reversed op slots
…icrosoft#8179)

Assisted by gh copilot.

Fix BitShiftRhs test input sets to avoid shift amounts >= bit width,
which is undefined behavior in C++ and can cause test failures as
expected values are computed via C++.
microsoft/hlsl-specs#791 splits the MulOp
operation into two distinct ops. Update the placeholder code to reflect
that.

Interesting changes are in `gen_intrin_main`, `hctdb.py`, and
`HLOperationLower.cpp`. The rest of the code is generated code
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