feat: copy rv32 base_alu, shift, mul, divrem to base_alu_w, shift_w, mul_w, divrem_w#2483
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shuklaayush merged 2 commits intodevelop-v1.8.0from Apr 17, 2026
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Resolves INT-6340, INT-6343. Summary: - `base_alu_w` and `shift_w` reuse the existing generic core AIRs (`BaseAluCoreAir<RV64_WORD_NUM_LIMBS, RV64_CELL_BITS>` and `ShiftCoreAir<RV64_WORD_NUM_LIMBS, RV64_CELL_BITS>`) via type aliases, eliminating the need for duplicated core code. - A new `Rv64BaseAluWAdapter` (`alu_w.rs`) bridges 64-bit register memory with the 4-byte core interface: it reads full 8-byte registers but only passes the low 4 bytes to the core, and sign-extends the 4-byte core output back to 8 bytes on write. - The test suite is largely carried over from the original RV32 code and primarily exercises the reused core AIR logic rather than the newly written adapter. --------- Co-authored-by: claude[bot] <41898282+claude[bot]@users.noreply.github.com> Co-authored-by: Ayush Shukla <shuklaayush@users.noreply.github.com> Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
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…mul_w, divrem_w (#2483) Towards INT-6340, INT-6341, INT-6342, INT-6343. This PR copies the RV32 `base_alu`, `shift`, `mul`, and `divrem` modules into new `base_alu_w`, `shift_w`, `mul_w`, and `divrem_w` modules. These copies will serve as the starting point for implementing the RV64 32-bit word instruction variants. --------- Co-authored-by: claude[bot] <41898282+claude[bot]@users.noreply.github.com> Co-authored-by: Ayush Shukla <shuklaayush@users.noreply.github.com> Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>
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Towards INT-6340, INT-6341, INT-6342, INT-6343.
This PR copies the RV32
base_alu,shift,mul, anddivremmodules into newbase_alu_w,shift_w,mul_w, anddivrem_wmodules. These copies will serve as the starting point for implementing the RV64 32-bit word instruction variants.