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15 changes: 15 additions & 0 deletions tests/component/conftest.py
Original file line number Diff line number Diff line change
Expand Up @@ -666,6 +666,21 @@ def do_port0_task(
return task


@pytest.fixture
def do_port0_task_32dio(
generate_task: Callable[[], nidaqmx.Task], real_x_series_device_32dio: nidaqmx.system.Device
) -> nidaqmx.Task:
"""Configure a single-channel DO task."""
task = generate_task()
# Select X Series port 0 32 lines
task.do_channels.add_do_chan(
real_x_series_device_32dio.do_ports[0].name,
line_grouping=LineGrouping.CHAN_FOR_ALL_LINES,
)
_start_do_task(task, is_port=True)
return task


@pytest.fixture
def do_port1_task(
generate_task: Callable[[], nidaqmx.Task], real_x_series_device: nidaqmx.system.Device
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Original file line number Diff line number Diff line change
Expand Up @@ -430,22 +430,22 @@ def test___digital_single_channel_writer___write_waveform_port_uint8___outputs_m


def test___digital_single_channel_writer___write_waveform_port_uint32___outputs_match_final_values(
do_port0_task: nidaqmx.Task,
di_port0_loopback_task: nidaqmx.Task,
do_port0_task_32dio: nidaqmx.Task,
di_port0_loopback_task_32dio: nidaqmx.Task,
) -> None:
writer = DigitalSingleChannelWriter(do_port0_task.out_stream)
writer = DigitalSingleChannelWriter(do_port0_task_32dio.out_stream)
# Since digital outputs don't have built-in loopback channels like analog outputs,
# we can only read back the last value. So to verify the whole signal, we must
# write waveforms of increasing length and verify the final value each time.
for i in range(1, 10):
num_samples = i
num_lines = 32
assert num_lines == _get_num_do_lines_in_task(do_port0_task)
assert num_lines == _get_num_do_lines_in_task(do_port0_task_32dio)
waveform = _create_digital_waveform_uint8(num_samples, num_lines)

samples_written = writer.write_waveform(waveform)

actual_value = di_port0_loopback_task.read()
actual_value = di_port0_loopback_task_32dio.read()
assert samples_written == num_samples
assert waveform.signal_count == num_lines
assert actual_value == _get_waveform_port_data(waveform)[i - 1]
8 changes: 4 additions & 4 deletions tests/component/task/test_task_write_waveform_do.py
Original file line number Diff line number Diff line change
Expand Up @@ -283,8 +283,8 @@ def test___task___write_waveform_port_uint8___outputs_match_final_values(


def test___task___write_waveform_port_uint32___outputs_match_final_values(
do_port0_task: nidaqmx.Task,
di_port0_loopback_task: nidaqmx.Task,
do_port0_task_32dio: nidaqmx.Task,
di_port0_loopback_task_32dio: nidaqmx.Task,
) -> None:
# Since digital outputs don't have built-in loopback channels like analog outputs,
# we can only read back the last value. So to verify the whole signal, we must
Expand All @@ -294,10 +294,10 @@ def test___task___write_waveform_port_uint32___outputs_match_final_values(
num_lines = 32
waveform = _create_digital_waveform_uint8(num_samples, num_lines)

samples_written = do_port0_task.write_waveform(waveform)
samples_written = do_port0_task_32dio.write_waveform(waveform)

assert samples_written == num_samples
actual_value = di_port0_loopback_task.read()
actual_value = di_port0_loopback_task_32dio.read()
assert actual_value == _get_waveform_port_data(waveform)[i - 1]


Expand Down