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[rtl] Expose lockstep and shadow bus interface core signals to ibex_top #2365

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Merged
nasahlpa merged 2 commits into from
Feb 10, 2026
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Merged

[rtl] Expose lockstep and shadow bus interface core signals to ibex_top #2365

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0de532c
[rtl] Expose lockstep and shadow bus interface core signals to ibex_top
nasahlpa Jan 22, 2026
afd13a5
[rtl] Exclude `data_wdata_intg` from lockstep comparison
nasahlpa Feb 5, 2026
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89 changes: 52 additions & 37 deletions doc/02_user/integration.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -113,55 +113,70 @@ Instantiation Template
.DmExceptionAddr ( 32'h1A110808 )
) u_top (
// Clock and reset
.clk_i (),
.rst_ni (),
.test_en_i (),
.scan_rst_ni (),
.ram_cfg_i (),
.clk_i (),
.rst_ni (),
.test_en_i (),
.scan_rst_ni (),
.ram_cfg_i (),

// Configuration
.hart_id_i (),
.boot_addr_i (),
.hart_id_i (),
.boot_addr_i (),

// Instruction memory interface
.instr_req_o (),
.instr_gnt_i (),
.instr_rvalid_i (),
.instr_addr_o (),
.instr_rdata_i (),
.instr_rdata_intg_i (),
.instr_err_i (),
.instr_req_o (),
.instr_gnt_i (),
.instr_rvalid_i (),
.instr_addr_o (),
.instr_rdata_i (),
.instr_rdata_intg_i (),
.instr_err_i (),

// Data memory interface
.data_req_o (),
.data_gnt_i (),
.data_rvalid_i (),
.data_we_o (),
.data_be_o (),
.data_addr_o (),
.data_wdata_o (),
.data_wdata_intg_o (),
.data_rdata_i (),
.data_rdata_intg_i (),
.data_err_i (),
.data_req_o (),
.data_gnt_i (),
.data_rvalid_i (),
.data_we_o (),
.data_be_o (),
.data_addr_o (),
.data_wdata_o (),
.data_wdata_intg_o (),
.data_rdata_i (),
.data_rdata_intg_i (),
.data_err_i (),

// Interrupt inputs
.irq_software_i (),
.irq_timer_i (),
.irq_external_i (),
.irq_fast_i (),
.irq_nm_i (),
.irq_software_i (),
.irq_timer_i (),
.irq_external_i (),
.irq_fast_i (),
.irq_nm_i (),

// Debug interface
.debug_req_i (),
.crash_dump_o (),
.debug_req_i (),
.crash_dump_o (),

// Special control signals
.fetch_enable_i (),
.alert_minor_o (),
.alert_major_internal_o (),
.alert_major_bus_o (),
.core_sleep_o ()
.fetch_enable_i (),
.alert_minor_o (),
.alert_major_internal_o (),
.alert_major_bus_o (),
.core_sleep_o (),

// Lockstep signals
.lockstep_cmp_en_o (),

// Shadow core data interface outputs
.data_req_shadow_o (),
.data_we_shadow_o (),
.data_be_shadow_o (),
.data_addr_shadow_o (),
.data_wdata_shadow_o (),
.data_wdata_intg_shadow_o (),

// Shadow core instruction interface outputs
.instr_req_shadow_o (),
.instr_addr_shadow_o ()
);

Parameters
Expand Down
17 changes: 16 additions & 1 deletion dv/formal/check/top.sv
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Expand Up @@ -110,7 +110,22 @@ module top import ibex_pkg::*; #(


// DFT bypass controls
input logic scan_rst_ni
input logic scan_rst_ni,

// Lockstep signals
output ibex_mubi_t lockstep_cmp_en_o,

// Shadow core data interface outputs
output logic data_req_shadow_o,
output logic data_we_shadow_o,
output logic [3:0] data_be_shadow_o,
output logic [31:0] data_addr_shadow_o,
output logic [31:0] data_wdata_shadow_o,
output logic [6:0] data_wdata_intg_shadow_o,

// Shadow core instruction interface outputs
output logic instr_req_shadow_o,
output logic [31:0] instr_addr_shadow_o
);

// Yosys based tools have no inherent understanding of a reset signal (unlike jasper, which has the
Expand Down
14 changes: 13 additions & 1 deletion dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -217,7 +217,19 @@ module ibex_riscv_compliance (
.alert_minor_o ( ),
.alert_major_internal_o ( ),
.alert_major_bus_o ( ),
.core_sleep_o ( )
.core_sleep_o ( ),

.lockstep_cmp_en_o ( ),

.data_req_shadow_o ( ),
.data_we_shadow_o ( ),
.data_be_shadow_o ( ),
.data_addr_shadow_o ( ),
.data_wdata_shadow_o ( ),
.data_wdata_intg_shadow_o ( ),

.instr_req_shadow_o ( ),
.instr_addr_shadow_o ( )
);

// SRAM block for instruction and data storage
Expand Down
13 changes: 12 additions & 1 deletion dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -170,7 +170,18 @@ module core_ibex_tb_top;
.alert_minor_o (dut_if.alert_minor ),
.alert_major_internal_o (dut_if.alert_major_internal),
.alert_major_bus_o (dut_if.alert_major_bus ),
.core_sleep_o (dut_if.core_sleep )
.core_sleep_o (dut_if.core_sleep ),

.lockstep_cmp_en_o ( ),
.data_req_shadow_o ( ),
.data_we_shadow_o ( ),
.data_be_shadow_o ( ),
.data_addr_shadow_o ( ),
.data_wdata_shadow_o ( ),
.data_wdata_intg_shadow_o ( ),

.instr_req_shadow_o ( ),
.instr_addr_shadow_o ( )
);

`define IBEX_RF_PATH core_ibex_tb_top.dut.u_ibex_top.gen_regfile_ff.register_file_i
Expand Down
14 changes: 13 additions & 1 deletion examples/simple_system/rtl/ibex_simple_system.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -274,7 +274,19 @@ module ibex_simple_system (
.alert_minor_o (),
.alert_major_internal_o (),
.alert_major_bus_o (),
.core_sleep_o ()
.core_sleep_o (),

.lockstep_cmp_en_o (),

.data_req_shadow_o (),
.data_we_shadow_o (),
.data_be_shadow_o (),
.data_addr_shadow_o (),
.data_wdata_shadow_o (),
.data_wdata_intg_shadow_o (),

.instr_req_shadow_o (),
.instr_addr_shadow_o ()
);

// SRAM block for instruction and data storage
Expand Down
32 changes: 28 additions & 4 deletions rtl/ibex_lockstep.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,7 @@ module ibex_lockstep import ibex_pkg::*; #(
input logic data_we_i,
input logic [3:0] data_be_i,
input logic [31:0] data_addr_i,
input logic [MemDataWidth-1:0] data_wdata_i,
input logic [31:0] data_wdata_i,
input logic [MemDataWidth-1:0] data_rdata_i,
input logic data_err_i,

Expand Down Expand Up @@ -108,7 +108,17 @@ module ibex_lockstep import ibex_pkg::*; #(
output logic alert_major_bus_o,
input ibex_mubi_t core_busy_i,
input logic test_en_i,
input logic scan_rst_ni
input logic scan_rst_ni,

output ibex_mubi_t lockstep_cmp_en_o,
output logic data_req_shadow_o,
output logic data_we_shadow_o,
output logic [3:0] data_be_shadow_o,
output logic [31:0] data_addr_shadow_o,
output logic [31:0] data_wdata_shadow_o,
output logic [6:0] data_wdata_intg_shadow_o,
output logic instr_req_shadow_o,
output logic [31:0] instr_addr_shadow_o
);

import prim_secded_pkg::SecdedInv3932ZeroWord;
Expand Down Expand Up @@ -329,7 +339,7 @@ module ibex_lockstep import ibex_pkg::*; #(
logic data_we;
logic [3:0] data_be;
logic [31:0] data_addr;
logic [MemDataWidth-1:0] data_wdata;
logic [31:0] data_wdata;
logic [IC_NUM_WAYS-1:0] ic_tag_req;
logic ic_tag_write;
logic [IC_INDEX_W-1:0] ic_tag_addr;
Expand Down Expand Up @@ -392,6 +402,10 @@ module ibex_lockstep import ibex_pkg::*; #(
logic shadow_dummy_instr_id;
logic shadow_dummy_instr_wb;

// The following output does not need to be checked in the lockstep comparison as we anyways
// check the data_wdata itself.
logic [6:0] shadow_data_wdata_intg;

///////////////////////////////
// Shadow core instantiation //
///////////////////////////////
Expand Down Expand Up @@ -458,7 +472,7 @@ module ibex_lockstep import ibex_pkg::*; #(
.data_we_o (shadow_outputs_d.data_we),
.data_be_o (shadow_outputs_d.data_be),
.data_addr_o (shadow_outputs_d.data_addr),
.data_wdata_o (shadow_outputs_d.data_wdata),
.data_wdata_o ({shadow_data_wdata_intg, shadow_outputs_d.data_wdata}),
.data_rdata_i (shadow_inputs_q[0].data_rdata),
.data_err_i (shadow_inputs_q[0].data_err),

Expand Down Expand Up @@ -641,4 +655,14 @@ module ibex_lockstep import ibex_pkg::*; #(
assign alert_major_bus_o = shadow_alert_major_bus;
assign alert_minor_o = shadow_alert_minor;

assign lockstep_cmp_en_o = enable_cmp_q;

assign data_req_shadow_o = shadow_outputs_d.data_req;
assign data_we_shadow_o = shadow_outputs_d.data_we;
assign data_be_shadow_o = shadow_outputs_d.data_be;
assign data_addr_shadow_o = shadow_outputs_d.data_addr;
assign data_wdata_shadow_o = shadow_outputs_d.data_wdata;
assign data_wdata_intg_shadow_o = shadow_data_wdata_intg;
assign instr_req_shadow_o = shadow_outputs_d.instr_req;
assign instr_addr_shadow_o = shadow_outputs_d.instr_addr;
endmodule
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