boards/arm/stm32h7: Add support for the NUCLEO-H723ZG board

Documentation/platforms/arm/stm32h7/boards/nucleo-h723zg/index.rst

@@ -0,0 +1,112 @@
+================
+ST Nucleo H723ZG
+================
+
+.. tags:: chip:stm32, chip:stm32h7, chip:stm32h723
+
+This page discusses issues unique to NuttX configurations for the
+STMicro Nucleo-H723ZG development board featuring the STM32H723ZG
+MCU. The STM32H723ZG is a up-to 550MHz Cortex-M7 operation with 1MByte Flash
+memory and 564KBytes of SRAM. The board features:
+
+- On-board ST-LINK/V2-1 for programming and debugging,
+- 3 user LEDs
+- Two pushbuttons (user and reset)
+- 32.768 kHz crystal oscillator
+- USB OTG HS with Micro-AB connector
+- Ethernet connector compliant with IEEE-802.3-2002
+- Board connectors:
+  - USB with Micro-AB
+  - SWD
+  - Ethernet RJ45
+  - ST Zio connector including Arduino Uno V3
+  - ST morpho
+
+Refer to the http://www.st.com website for further information about this
+board (search keyword: Nucleo-H723ZG)
+
+Serial Console
+==============
+
+Many options are available for a serial console via the Morpho connector.
+Here two common serial console options are suggested:
+
+1. Arduino Serial Shield.
+
+   If you are using a standard Arduino RS-232 shield with the serial
+   interface with RX on pin D0 and TX on pin D1 from USART6:
+
+      ======== ========= =====
+      ARDUINO  FUNCTION  GPIO
+      ======== ========= =====
+      DO RX    USART6_RX PG9
+      D1 TX    USART6_TX PG14
+      ======== ========= =====
+
+2. Nucleo Virtual Console.
+
+   The virtual console uses Serial Port 3 (USART3) with TX on PD8 and RX on
+   PD9.
+
+      ================= ===
+      VCOM Signal       Pin
+      ================= ===
+      SERIAL_RX         PD9
+      SERIAL_TX         PD8
+      ================= ===
+
+   These signals are internally connected to the on board ST-Link.
+
+   The Nucleo virtual console is the default serial console in all
+   configurations unless otherwise stated in the description of the
+   configuration.
+
+Configurations
+==============
+
+Information Common to All Configurations
+----------------------------------------
+
+Each Nucleo-H723ZG configuration is maintained in a sub-directory and
+can be selected as follow::
+
+    tools/configure.sh [options] nucleo-h723zg:<subdir>
+
+Where options should specify the host build platform (-l for Linux, -c for
+Cygwin under Windows, etc.).  Try ``tools/configure.sh -h`` for the complete
+list of options.
+
+Before starting the build, make sure that (1) your PATH environment variable
+includes the correct path to your toolchain, and (2) you have the correct
+toolchain selected in the configuration.
+
+And then build NuttX by simply typing the following.  At the conclusion of
+the make, the nuttx binary will reside in an ELF file called, simply, nuttx.::
+
+    make
+
+Configuration Sub-directories
+=============================
+
+nsh:
+----
+
+This configuration provides a basic NuttShell configuration (NSH)
+for the Nucleo-H723ZG.  The default console is the VCOM on USART3.
+
+netnsh:
+--------
+
+This configuration enables support for the Ethernet and a set
+of networking functionalities.
+
+.. NOTE::
+    The initialization logic waits for Ethernet auto negotiation to complete
+    up to a timeout. The timeout is a number of times the MII status register
+    is read from the PHY. First to verify the link status is up, subsequently
+    to verify the auto negotiation is complete. The timeout is set to a fixed
+    value of ``PHY_RETRY_TIMEOUT=0x1998``.
+    In each cycle the program waits for ``nxsched_usleep(100)``. By default
+    this gets rounded up to the value of the tick time which is 10 ms!
+    Therefore the time you will wait for the nsh console if the Ethernet
+    is not plugged in is ``2 * 10 ms * 0x1998 = 130s``.

arch/arm/include/stm32h7/chip.h

@@ -55,7 +55,9 @@
  * overridden with CONFIG_STM32H7_FLASH_OVERRIDE_x
  */
 
-#if defined (CONFIG_ARCH_CHIP_STM32H743AG) || \
+#if defined (CONFIG_ARCH_CHIP_STM32H723VG) || \
+    defined (CONFIG_ARCH_CHIP_STM32H723ZG) || \
+    defined (CONFIG_ARCH_CHIP_STM32H743AG) || \
     defined (CONFIG_ARCH_CHIP_STM32H743AI) || \
     defined (CONFIG_ARCH_CHIP_STM32H743BG) || \
     defined (CONFIG_ARCH_CHIP_STM32H743BI) || \
@@ -91,12 +93,21 @@
 #if defined(CONFIG_STM32H7_STM32H7X0XX) || defined(CONFIG_STM32H7_STM32H7X3XX) || defined(CONFIG_STM32H7_STM32H7X5XX)
 /* Memory */
 
+#  ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX
+#    define STM32H7_SRAM_SIZE             (320*1024)  /* 320Kb SRAM on AXI bus Matrix (D1) */
+#    define STM32H7_SRAM1_SIZE            (16*1024)   /*  16Kb SRAM1 on AHB bus Matrix (D2) */
+#    define STM32H7_SRAM2_SIZE            (16*1024)   /*  16Kb SRAM2 on AHB bus Matrix (D2) */
+#    define STM32H7_SRAM3_SIZE            (0*1024)    /*    No SRAM3 on AHB bus Matrix (D2) */
+#    define STM32H7_SRAM123_SIZE          (32*1024)   /*  32Kb SRAM123 on AHB bus Matrix (D2) */
+#    define STM32H7_SRAM4_SIZE            (16*1024)   /*  16Kb SRAM4 on AHB bus Matrix (D3) */
+#  else /* STM32H74XXX or STM32H75XXX with full SRAM configuration  */
 #    define STM32H7_SRAM_SIZE             (512*1024)  /* 512Kb SRAM on AXI bus Matrix (D1) */
 #    define STM32H7_SRAM1_SIZE            (128*1024)  /* 128Kb SRAM1 on AHB bus Matrix (D2) */
 #    define STM32H7_SRAM2_SIZE            (128*1024)  /* 128Kb SRAM2 on AHB bus Matrix (D2) */
 #    define STM32H7_SRAM3_SIZE            (32*1024)   /*  32Kb SRAM3 on AHB bus Matrix (D2) */
 #    define STM32H7_SRAM123_SIZE          (288*1024)  /* 128Kb SRAM123 on AHB bus Matrix (D2) */
 #    define STM32H7_SRAM4_SIZE            (64*1024)   /*  64Kb SRAM2 on AHB bus Matrix (D3) */
+#  endif /* STM32H72XXX or STM32H73XXX / STM32H74XXX or STM32H75XXX */
 #  if defined(CONFIG_ARMV7M_HAVE_DTCM)
 #      define STM32H7_DTCM_SRAM_SIZE      (128*1024)  /* 128Kb DTCM SRAM on TCM interface */
 #  else

arch/arm/include/stm32h7/stm32h7x3xx_irq.h

@@ -200,13 +200,26 @@
 #define STM32_IRQ_LPUART       (STM32_IRQ_FIRST + 142)  /* 142: LPUART global interrupt */
 #define STM32_IRQ_WWDG1RST     (STM32_IRQ_FIRST + 143)  /* 143: Window Watchdog interrupt */
 #define STM32_IRQ_CRS          (STM32_IRQ_FIRST + 144)  /* 144: Clock Recovery System global interrupt */
-#define STM32_IRQ_RESERVED145  (STM32_IRQ_FIRST + 145)  /* 145: Reserved */
+#define STM32_IRQ_ECC          (STM32_IRQ_FIRST + 145)  /* 145: Reserved */
 #define STM32_IRQ_SAI4         (STM32_IRQ_FIRST + 146)  /* 146: SAI4  global interrupt */
-#define STM32_IRQ_RESERVED147  (STM32_IRQ_FIRST + 147)  /* 147: Reserved */
+#define STM32_IRQ_DTS          (STM32_IRQ_FIRST + 147)  /* 147: Reserved */
 #define STM32_IRQ_RESERVED148  (STM32_IRQ_FIRST + 148)  /* 148: Reserved */
 #define STM32_IRQ_WKUP         (STM32_IRQ_FIRST + 149)  /* 149: WKUP1 to WKUP6 pins */
+#define STM32_IRQ_OCTOSPI2     (STM32_IRQ_FIRST + 150)  /* 150: OCTOSPI2 */
+#define STM32_IRQ_RESERVED151  (STM32_IRQ_FIRST + 151)  /* 151: Reserved */
+#define STM32_IRQ_RESERVED152  (STM32_IRQ_FIRST + 152)  /* 152: Reserved */
+#define STM32_IRQ_FMAC         (STM32_IRQ_FIRST + 153)  /* 153: FMAC */
+#define STM32_IRQ_CORDIC       (STM32_IRQ_FIRST + 154)  /* 154: CORDIC */
+#define STM32_IRQ_UART9        (STM32_IRQ_FIRST + 155)  /* 155: UART9 */
+#define STM32_IRQ_USART10      (STM32_IRQ_FIRST + 156)  /* 156: USART10 */
+#define STM32_IRQ_I2C5_EV      (STM32_IRQ_FIRST + 157)  /* 157: I2C5 Event */
+#define STM32_IRQ_I2C5_ER      (STM32_IRQ_FIRST + 158)  /* 158: I2C5 Error */
+#define STM32_IRQ_FDCAN3_0     (STM32_IRQ_FIRST + 159)  /* 159: FDCAN3 Interrupt 0 */
+#define STM32_IRQ_FDCAN3_1     (STM32_IRQ_FIRST + 160)  /* 160: FDCAN3 Interrupt 1 */
+#define STM32_IRQ_TIM23        (STM32_IRQ_FIRST + 161)  /* 161: TIM23 global */
+#define STM32_IRQ_TIM24        (STM32_IRQ_FIRST + 162)  /* 162: TIM24 global */
 
-#define STM32_IRQ_NEXTINTS     150
+#define STM32_IRQ_NEXTINTS     163
 #define NR_IRQS                (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
 
 #endif /* __ARCH_ARM_INCLUDE_STM32H7_STM32H7X3XX_IRQ_H */

arch/arm/src/stm32h7/Kconfig

@@ -12,6 +12,32 @@ choice
 	default ARCH_CHIP_STM32H743ZI
 	depends on ARCH_CHIP_STM32H7
 
+config ARCH_CHIP_STM32H723VG
+	bool "STM32H723VG"
+	select STM32H7_STM32H7X3XX
+	select STM32H7_STM32H72XXX_OR_STM32H73XXX
+	select STM32H7_FLASH_CONFIG_G
+	select STM32H7_IO_CONFIG_V
+	select STM32H7_HAVE_FDCAN1
+	select STM32H7_HAVE_FDCAN2
+	select STM32H7_HAVE_FDCAN3
+	---help---
+		STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM,
+		LQFP144
+
+config ARCH_CHIP_STM32H723ZG
+	bool "STM32H723ZG"
+	select STM32H7_STM32H7X3XX
+	select STM32H7_STM32H72XXX_OR_STM32H73XXX
+	select STM32H7_FLASH_CONFIG_G
+	select STM32H7_IO_CONFIG_Z
+	select STM32H7_HAVE_FDCAN1
+	select STM32H7_HAVE_FDCAN2
+	select STM32H7_HAVE_FDCAN3
+	---help---
+		STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM,
+		LQFP144
+
 config ARCH_CHIP_STM32H743AG
 	bool "STM32H743AG"
 	select STM32H7_STM32H7X3XX
@@ -491,6 +517,11 @@ config STM32H7_STM32H7X7XX
 	select STM32H7_HAVE_SPI6
 	select STM32H7_HAVE_RNG
 
+# The reduced SRAM configuration STM32H72X and STM32H73X
+config STM32H7_STM32H72XXX_OR_STM32H73XXX
+	bool
+	default n
+
 config STM32H7_FLASH_CONFIG_B
 	bool
 	default n
@@ -700,6 +731,10 @@ config STM32H7_HAVE_FDCAN2
 	bool
 	default n
 
+config STM32H7_HAVE_FDCAN3
+	bool
+	default n
+
 config STM32H7_HAVE_RNG
 	bool
 	default n
@@ -938,6 +973,11 @@ config STM32H7_FDCAN2
 	default n
 	select STM32H7_FDCAN
 
+config STM32H7_FDCAN3
+	bool "FDCAN3"
+	default n
+	select STM32H7_FDCAN
+
 endmenu # STM32H7 FDCAN Selection
 
 menu "STM32H7 I2C Selection"
@@ -6394,7 +6434,7 @@ endchoice # Input channel event count
 endmenu # QEncoder Driver
 
 menu "FDCAN Driver Configuration"
-	depends on STM32H7_FDCAN1 || STM32H7_FDCAN2
+	depends on STM32H7_FDCAN1 || STM32H7_FDCAN2 || STM32H7_FDCAN3
 
 menu "FDCAN1 Configuration"
 	depends on STM32H7_FDCAN1
@@ -6436,6 +6476,26 @@ config FDCAN2_DATA_BITRATE
 
 endmenu # STM32H7_FDCAN2
 
+menu "FDCAN3 Configuration"
+	depends on STM32H7_FDCAN3
+
+config FDCAN3_BITRATE
+	int "CAN bitrate"
+	depends on !NET_CAN_CANFD
+	default 1000000
+
+config FDCAN3_ARBI_BITRATE
+	int "CAN FD Arbitration phase bitrate"
+	depends on NET_CAN_CANFD
+	default 1000000
+
+config FDCAN3_DATA_BITRATE
+	int "CAN FD Data phase bitrate"
+	depends on NET_CAN_CANFD
+	default 4000000
+
+endmenu # STM32H7_FDCAN3
+
 config STM32H7_FDCAN_REGDEBUG
 	bool "Enable register dump debugging"
 	depends on DEBUG_NET_INFO

arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h

@@ -64,9 +64,13 @@
 #define STM32_AXISRAM_BASE   0x24000000     /* 0x24000000-0x247fffff: System AXI SRAM */
 
 #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
-#  define STM32_SRAM1_BASE   0x30000000     /* 0x30000000-0x3001ffff: System SRAM1 */
+#  define STM32_SRAM1_BASE   0x30000000     /* 0x30000000-0x30003fff: System SRAM1 */
+#  ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX
+#  define STM32_SRAM2_BASE   0x30004000     /* 0x30004000-0x30007fff: System SRAM2 */
+#  else /* STM32H74XXX or STM32H75XXX with full SRAM configuration  */
 #  define STM32_SRAM2_BASE   0x30020000     /* 0x30020000-0x3003ffff: System SRAM2 */
 #  define STM32_SRAM3_BASE   0x30040000     /* 0x30040000-0x30047fff: System SRAM3 */
+#  endif /* STM32H72XXX or STM32H73XXX / STM32H74XXX or STM32H75XXX */
 #  define STM32_SRAM123_BASE 0x30000000     /* 0x30000000-0x30047fff: System SRAM123 */
 #else
 

arch/arm/src/stm32h7/stm32_fdcan_sock.c

@@ -353,7 +353,6 @@ static const struct fdcan_config_s stm32_fdcan1_config =
 #endif
 
 #ifdef CONFIG_STM32H7_FDCAN3
-#  error "FDCAN3 support not yet added to stm32h7x3xx header files (pinmap, irq, etc.)"
 static const struct fdcan_config_s stm32_fdcan2_config =
 {
   .tx_pin      = GPIO_CAN3_TX,
@@ -2499,7 +2498,7 @@ int stm32_fdcansockinitialize(int intf)
 
 #ifdef CONFIG_STM32H7_FDCAN3
     case 2:
-      priv             = &g_fdcan2
+      priv             = &g_fdcan2;
       memset(priv, 0, sizeof(struct fdcan_driver_s));
       priv->base       = STM32_FDCAN3_BASE;
       priv->iface_idx  = 2;

arch/arm/src/stm32h7/stm32_irq.c

@@ -322,8 +322,40 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
           *bit     = 1 << (extint - 128);
         }
       else
+#elif STM32_IRQ_NEXTINTS <= 192
+      if (extint < 32)
+        {
+          *regaddr = (NVIC_IRQ0_31_ENABLE + offset);
+          *bit     = 1 << extint;
+        }
+      else if (extint < 64)
+        {
+          *regaddr = (NVIC_IRQ32_63_ENABLE + offset);
+          *bit     = 1 << (extint - 32);
+        }
+      else if (extint < 96)
+        {
+          *regaddr = (NVIC_IRQ64_95_ENABLE + offset);
+          *bit     = 1 << (extint - 64);
+        }
+      else if (extint < 128)
+        {
+          *regaddr = (NVIC_IRQ96_127_ENABLE + offset);
+          *bit     = 1 << (extint - 96);
+        }
+      else if (extint < 160)
+        {
+          *regaddr = (NVIC_IRQ128_159_ENABLE + offset);
+          *bit     = 1 << (extint - 128);
+        }
+      else if (extint < STM32_IRQ_NEXTINTS)
+        {
+          *regaddr = (NVIC_IRQ160_191_ENABLE + offset);
+          *bit     = 1 << (extint - 160);
+        }
+      else
 #else
-#  warning Missing logic
+#  error Missing logic
 #endif
         {
           return ERROR; /* Invalid interrupt */

boards/Kconfig

@@ -1915,6 +1915,15 @@ config ARCH_BOARD_WEACT_STM32H750
 	---help---
 		This is WeAct MiniSTM32H7xx (STM32H750VB) board.
 
+config ARCH_BOARD_NUCLEO_H723ZG
+	bool "STM32H723 Nucleo H723ZG"
+	depends on ARCH_CHIP_STM32H723ZG
+	select ARCH_HAVE_LEDS
+	select ARCH_HAVE_BUTTONS
+	select ARCH_HAVE_IRQBUTTONS
+	---help---
+		STMicro Nucleo H723ZG board based on the STMicro STM32H723ZG MCU.
+
 config ARCH_BOARD_NUCLEO_H743ZI
 	bool "STM32H743 Nucleo H743ZI"
 	depends on ARCH_CHIP_STM32H743ZI
@@ -3699,6 +3708,7 @@ config ARCH_BOARD
 	default "nucleo-g0b1re"                if ARCH_BOARD_NUCLEO_G0B1RE
 	default "weact-stm32h743"              if ARCH_BOARD_WEACT_STM32H743
 	default "weact-stm32h750"              if ARCH_BOARD_WEACT_STM32H750
+	default "nucleo-h723zg"                if ARCH_BOARD_NUCLEO_H723ZG
 	default "nucleo-h743zi"                if ARCH_BOARD_NUCLEO_H743ZI
 	default "nucleo-h743zi2"               if ARCH_BOARD_NUCLEO_H743ZI2
 	default "nucleo-h745zi"                if ARCH_BOARD_NUCLEO_H745ZI
@@ -4435,6 +4445,9 @@ endif
 if ARCH_BOARD_WEACT_STM32H750
 source "boards/arm/stm32h7/weact-stm32h750/Kconfig"
 endif
+if ARCH_BOARD_NUCLEO_H723ZG
+source "boards/arm/stm32h7/nucleo-h723zg/Kconfig"
+endif
 if ARCH_BOARD_NUCLEO_H743ZI
 source "boards/arm/stm32h7/nucleo-h743zi/Kconfig"
 endif