cpubits: add 64-bit override for ARMv7 #1419
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ARMv7 is one of the main architectures for which we've received requests for 64-bit overrides in the past (see discussion on #826). Though natively 32-bit, ARMv7 supports certain "doubleword" instructions which model 64-bit values as a pair of 32-bit registers, e.g. `ADDS`/`ADC` and `SUBS`/`SBC` for 2x32-bit addition/subtraction, as well as `UMULL`/`SMULL` for widening multiplication with 64-bit outputs. Many ARMv7 CPUs internally fetch 64-bits of instruction at once and can move 64-bits of data via `LDRD`/`STRD` in one cycle on optimized paths. Some high-performance ARMv7 CPUs internally combine the barrel shifter + ALU to speed multi-word shifts. If we use 64-bit implementations when targeting ARMv7, codegen is able to leverage these optimizations.
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ARMv7 is one of the main architectures for which we've received requests for 64-bit overrides in the past (see discussion on #826).
Though natively 32-bit, ARMv7 supports certain "doubleword" instructions which model 64-bit values as a pair of 32-bit registers, e.g.
ADDS/ADCandSUBS/SBCfor 2x32-bit addition/subtraction, as well asUMULL/SMULLfor widening multiplication with 2x32-bit outputs.Many ARMv7 CPUs internally fetch 64-bits of instruction at once and can move 64-bits of data via
LDRD/STRDin one cycle on optimized paths.Some high-performance ARMv7 CPUs internally combine the barrel shifter + ALU to speed multi-word shifts.
If we use 64-bit implementations when targeting ARMv7, codegen is able to leverage these optimizations.