cpufeatures: add support for risc-v

[come-maiz]

I'm trying to build the lighthouse ethereum client in a risc-v unmatched board, and it fails with:

Compiling cpufeatures v0.2.12
error: This crate works only on `aarch64`, `loongarch64`, `x86`, and `x86-64` targets.
   --> /home/come-maiz/.cargo/registry/src/index.crates.io-6f17d22bba15001f/cpufeatures-0.2.12/src/lib.rs:152:1
    |
152 | compile_error!("This crate works only on `aarch64`, `loongarch64`, `x86`, and `x86-64` targets.");
    | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

> uname -a
Linux ubuntu 6.8.0-31-generic #31.1-Ubuntu SMP PREEMPT_DYNAMIC Sun Apr 21 01:12:53 UTC 2024 riscv64 riscv64 riscv64 GNU/Linux

Please add support for the risc-v architecture.

[tarcieri]

I think the culprit in your project is the ethereum_hashing crate, which is unconditionally linking cpufeatures, but only actually using it on x86_64: https://github.com/sigp/ethereum_hashing/blob/b6b5ff2/Cargo.toml#L15

See here for usage: https://github.com/sigp/ethereum_hashing/blob/b6b5ff2d8db972ee6453a710e82aee3c638d5d82/src/lib.rs#L130

The real solution to your immediate problem is to open an issue on the ethereum_hashing crate and request they gate their usage of cpufeatures to x86_64 targets, similar to this (but removing the ARM CPUs): https://github.com/RustCrypto/block-ciphers/blob/2c3de88/aes/Cargo.toml#L20

We can leave this issue open to discuss prospective RISC-V support, but my understanding is it would require complex OS interactions similar to ARM because the runtime CPU feature detection instructions are protected.

[come-maiz]

Thanks for all the details @tarcieri. I think we will have it fixed in lighthouse soon :)

I have access to a few riscv boards, so with patience and guidance I can contribute adding support in cpufeatures. I'll start by studying more about these boards.

[newpavlov]

IIUC you have to use the riscv_hwprobe syscall for this. Currently it's not exposed in libc, so you have to use raw asm!-based code for calling it. Obviously, it will be a Linux-only solution. Number of exposed extensions is quite small, so I am not sure it's worth to bother with it at the current moment.

[lazyprogrammerio]

IIUC you have to use the riscv_hwprobe syscall for this. Currently it's not exposed in libc, so you have to use raw asm!-based code for calling it. Obviously, it will be a Linux-only solution. Number of exposed extensions is quite small, so I am not sure it's worth to bother with it at the current moment.

https://github.com/rust-lang/libc/blob/main/src/unix/linux_like/linux/gnu/b64/riscv64/mod.rs#L549C11-L549C29 seems that it is already being exposed.

[newpavlov]

seems that it is already being exposed.

I meant the libc crate.

[MuntasirSZN]

Is this being worked on? I would also like risc-v support..

[MuntasirSZN]

To my digging, there is no other way (I guess) of getting ISA info other than misa instruction which exposes only the first letter of supported isa name, but not the things after. So we know for example Z family is there but don't know if Zbc is available. As its no_std, libc is no go?

[newpavlov]

As noted above, there is a Linux-specific way of retrieving features supported by CPU. We use something similar for Linux and Mac AArch64 targets.

But I am not sure we should implement this logic as part of this crate. I am thinking about using std::arch::is_*_feature_detected on targets where we know std is available and fall back to compile time detection on other targets unless std crate feature is enabled.