OpenLake x FOSSI

FOSSi — Free Open Source Silicon Society
Credits: Rishik Ram J, IIT Bhilai '22

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1. Core Focus Areas

ASIC / FPGA Development

Front-End Design

• RTL Design Languages
  • Verilog (HDL)
  • Amaranth
  • Chisel (Hardware Construction Language / HCL)
• Verification
  • Simulation
    • Open-Source: Verilator, Icarus Verilog (iverilog)
    • Proprietary: Synopsys VCS, Cadence Xelium
  • Formal Verification
    • Open-Source: SymbiYosys
    • Proprietary: Jasper, VC Formal

Back-End Design

• FPGA
  • Understanding Architecture
  • Implementation Flow (Refer to slide 16+ for extended details):
    1. Synthesis
    2. Place and Route
    3. Bitstream Generation
• ASIC
  • Digital Design (Physical Design — RTL to GDS)
    • Synthesis
    • Floorplanning & Chip Design
    • Placement
    • Clock Tree Synthesis (CTS)
    • Parasitic Extraction
    • Routing
    • DRC / LVS Checks
    • GDS Generation
  • Analog Design & PDK
    • RF & Custom IC Design
    • Memory Layout
    • Understanding PDKs (Process Design Kits)
    • Basic Reference: AICD Analog Circuit Design Guide

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Verilog to GDSII Learning Map

Ten phases. Each phase gives resources, practicals .

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The Ten Phases

#	Phase	Time
00	Set Up The Toolchain
01	Verilog Language Core
02	Testbench And Verification
03	FPGA Flow And Bitstream Generation
04	RTL To GDS - First Full Run
05	Constraints, Clocks And Timing
06	Synthesis, Floorplan And Power
07	Placement, CTS And Routing
08	Signoff - STA, DRC, LVS And GDS
09	Tapeout On Real Silicon

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00 — Set Up The Toolchain

All members use the same tools. Do this before any other phase.

Resources

• OSS CAD Suite - one download, all open tools
• Icarus Verilog simulator
• Verilator - fast C++ simulator
• Surfer waveform viewer (modern GTKWave)
• GTKWave waveform viewer
• EDA Playground - browser only, zero install

Practicals

• Install OSS CAD Suite. Run yosys -V and iverilog -V.
• Write blink.v. Simulate it with Icarus Verilog.
• Open the VCD file in Surfer or GTKWave.

Please Open issue if you are not able to setup or facing any issues !

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01 — Verilog Language Core

Read and write synthesisable Verilog

• Combinational Logic
• Sequential Logic
• state machines etc..
• Following HDLBits constructs

Resources

• HDLBits - the main practice engine
• ASIC World Verilog tutorial - full language tour
• ChipVerify Verilog tutorial
• Nandland - beginner Verilog with real examples
• ETH Zurich Digital Design and Computer Architecture (free lectures)
• Cornell ECE 4750 - computer architecture with RTL labs
• Book: Verilog HDL by Samir Palnitkar
• HDLBits solution notes (community gitbook)
• [Learning FPGA, yosys, nextpnr, and RISC-V] (https://github.com/BrunoLevy/learn-fpga)
• [Verilog Wizards by Stuart Sutherland ] (https://sutherland-hdl.com/papers.html)
• [FPGACPU.CA ] (https://fpgacpu.ca/)
• zipcpu verilog tutorials
• Verilog Pro
• Programming Open Source FPGAs

Direction

• complete HDLBits Verilog Language section
• complete HDLBits Circuits section.
  • Combinational first
  • sequential
  • FSM etc ..
• Do the Verification: Reading Simulations section. It teaches debug.
• examples to build :
  • 4-bit counter
  • frequency divider
  • shift register
  • gray code counter
  • one-hot FSM
  • synchronous FIFO.

We can make a weekly HDLBits sprint

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02 — Testbench And Verification

Prove that the design is correct. Do not trust the eye.

Resources

• cocotb - write testbenches in Python
• Verilator manual - lint and coverage
• SymbiYosys (sby) - formal verification
• SymbiYosys documentation
• Verilator book - simulation with C++
• Tiny Tapeout Verilog template - has cocotb CI built in

Practicals

• Write a self-checking testbench for the FIFO. It must fail loudly on error.
• Convert one testbench to cocotb.
• Run verilator --lint-only on every design. Fix all warnings.
• Write one formal property with sby. Example: the FIFO never overflows.

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03 — FPGA Flow And Bitstream

Move RTL to real hardware. See the LED blink.

FPGA FLOW

• Synthesis

• Placement

• Routing (Fix the timing if you have any )

• Bitstream generation

• FLash on FPGA

• Use this for reference on the board I am going to share

Resources

• Yosys - open synthesis
• nextpnr - open place and route
• openFPGALoader - universal bitstream loader

Practicals

OpenSource FPGA Flow

• Take any fpga board for the group. Good options: Tang Nano 9K (low cost), iCEBreaker, ULX3S.(for opensource ) , same flow for the xilinix fpgas if you have
• Run the four steps by hand:
  • yosys - synthesis
  • nextpnr, packer : Placement and Routing
  • openFPGALoader - Flash bitstream
• Write a Makefile for the four steps. Share it in the community repo.
• Flash the frequency divider. Prove the LED rate with a scope or a counter.
• Build a UART transmitter. Print Hello from the FPGA to a terminal.
• Read the nextpnr timing report. Find the critical path.

Community Job

Start a board pool. One board serves four members by post or by a remote JTAG host. Record a 60 second demo video for each flash.

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Practicals

• Write an SDC file. Set create_clock, input_delay and output_delay.
• Run OpenSTA on a synthesised netlist. Read the worst negative slack.
• Break the timing on purpose. Add a long combinational chain. Watch the slack go negative.
• Fix the timing with a pipeline register. Compare the two reports.

Community Job

Hold one whiteboard session. Each member draws a setup and a hold violation. Post the photos to the wiki.

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04 — RTL To GDS - First Full Run

Get one GDSII file. Do not study each step yet. Get the win first.

Resources

• LibreLane - successor to OpenLane 2, FOSSi Foundation
• LibreLane tutorial (UCSC VLSI-DA)
• OpenROAD Flow Scripts (ORFS)
• ORFS full RTL to GDS tutorial
• SkyWater SKY130 open PDK
• SKY130 PDK documentation
• open_pdks - builds the PDK for the tools
• ChipFoundry OpenLane 2 fork

Practicals

• Install LibreLane with Nix. Follow the getting started guide.
• Run the built-in spm design (serial parallel multiplier). It is the standard first example.
• Open the final GDS in KLayout. Zoom to a single standard cell.

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05 — Synthesis, Floorplan And Power

Open the black box. Study the first half of the flow.

Resources

• Yosys manual - synthesis internals
• OpenROAD floorplan and PDN commands
• VSD Advanced Physical Design using OpenLANE/Sky130 (paid workshop)
• Community VSD workshop notes - free and detailed
• Second community notes set

Practicals

• Run yosys alone on the frequency divider. Read the gate level netlist.
• Use the yosys show command. Look at the mapped gates.
• Change the core utilisation from 0.4 to 0.7. Rerun. Compare the die area.
• Change the aspect ratio. See the effect on the floorplan.
• View the power distribution network in KLayout. Trace one power strap.
• Break the PDN on purpose. Read the error. Then fix it.

06 — Constraints, Clocks And Timing

Understand setup, hold and the clock tree. This is the bridge to ASIC.

Resources

• OpenSTA - open static timing analysis
• OpenROAD documentation - timing commands
• SDC constraint basics (ChipVerify STA)

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Loop Back and fix the synthesis timing file

07 — Placement, CTS And Routing

Study the second half of the flow. Watch the design become physical.

Resources

• OpenROAD - place, CTS and route engines
• OpenROAD GUI guide - step through each stage
• TritonRoute detailed routing (inside OpenROAD)
• KLayout layout viewer

Practicals

• Open the OpenROAD GUI. Load the design after each stage.
• Find the clock tree after CTS. Measure the clock skew in the report.
• Count the buffers that CTS added. Compare with the pre-CTS netlist.
• Look at the routing congestion heat map. Find the hot region.
• Force congestion. Set utilisation to 0.85. Read the failure.

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08 — Signoff - STA, DRC, LVS And GDS

Prove the layout is correct and manufacturable.

Resources

• Magic - layout, DRC and extraction
• Netgen - LVS comparison
• KLayout DRC decks
• OpenSTA - multi corner signoff timing
• SKY130 rule documentation

Practicals

• Run DRC in Magic and in KLayout. Compare the two reports.
• Run LVS with Netgen. Read the device count match.
• Add a deliberate DRC error. Example: make one metal spacing too small. Find it again.
• Run multi corner STA. Read the slow corner and the fast corner.
• Export the GDS. Check the layer count and the file size.

Community Job

Build a shared error dictionary. Each new DRC or LVS message goes in the wiki with the fix. This is the highest value community asset.

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09 — Tapeout On Real Silicon

Send a design to a real fab. The community gets real chips.

Resources

• Tiny Tapeout - the cheapest route to silicon
• Tiny Tapeout shuttle list and dates
• Tiny Tapeout Verilog template
• Zero to ASIC Course - guided tapeout, includes a tile
• ChipFoundry platform - SKY130 shuttles
• Caravel user project template
• wafer.space - GF180MCU runs
• IHP Open PDK - open 130nm from Europe
• GF180MCU open PDK
• FOSSi Foundation - news and governance
• fossi-chat.org - the main community chat

Practicals

• Fork the Tiny Tapeout template. Fit your design in one tile.
• Pass the GitHub Actions checks. They run the full GDS flow.
• Submit to the open shuttle before the close date.
• Design the test plan now. You will get the chip many months later.
• Build the demo board or use the Tiny Tapeout demo PCB.

Design Ladder

Use the same designs across phases. The design gets harder. The flow stays the same.

Design	Used in	Why it earns a place
Frequency divider	Phase 01, 03, 06	Simplest clocked design. Good first FPGA and first GDS.
Serial parallel multiplier (spm)	Phase 05	The standard LibreLane example. Small and complete.
4-bit and 8-bit counter	Phase 01, 03	Teaches reset style and enable logic.
Shift register and LFSR	Phase 01, 03	Teaches sequential structure and pseudo random data.
Synchronous FIFO	Phase 02	Teaches pointers, full and empty flags, and self-checking tests.
UART transmit and receive	Phase 03	First useful hardware. Connects to a PC terminal.
SPI master	Phase 03	Teaches protocol timing and external devices.
Simple ALU	Phase 01, 06	Teaches area and timing trade-offs in synthesis.
GCD accelerator	Phase 05	The ORFS reference design. Good for flow comparison.
PicoRV32 or Ibex core	Phase 06 to 08	A real CPU. Large enough to show congestion and CTS effects.
Tiny Tapeout tile project	Phase 09	The final group deliverable.

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