[Feature] Support Intern-S2-Preview training on NPU

[CyCle1024]

Summary

This PR adds NPU training support for Intern-S2-Preview while keeping the shared model and CUDA operator contracts stable.

• Improve MTP recomputation, FSDP scheduling, parameter residency, and LM-head prefetch control.
• Preserve device Tensor sequence boundaries and pass NPU CPU-list metadata through explicit parameters.
• Add Triton-Ascend fused cross-entropy for large-vocabulary training.
• Skip tail-padding tokens in the standard MoE dispatch path and cache the required indices.
• Add self-contained NPU GatedDeltaNet causal-convolution, gated-delta-rule, RMSNormGated, metadata, and sequence-parallel support.
• Integrate NPU CPU-affinity binding into the trainer lifecycle and retain host IRQ configuration helpers.
• Remove the dependency on a version-specific private DTensor shard API.

Design notes

• Public cumulative-length arguments remain device tensors. NPU-only CPU lists and chunk metadata use separate, explicit parameters, so CUDA kernels do not receive Python lists.
• GatedDeltaNet uses [B, T, H, D] as its public layout. The NPU wrappers preserve native head-first storage with transpose views where possible and materialize only when required by a fixed-layout kernel.
• Normal GatedDeltaNet forward keeps one mixed-QKV convolution. Sequence-parallel forward gathers the global packed-token axis, shards heads, and runs separate Q/K/V convolutions, matching the NPU kernel geometry.
• GatedDeltaNet metadata is prepared once per sequence context and reused across layers. Cache reuse requires identical cumulative sequence boundaries, device, token count, and kernel block configuration.
• Backend-specific implementations and dispatch stay under xtuner/v1/ops; model modules keep device-independent logical interfaces.
• CUDA keeps its existing tensor inputs, loss-reduction behavior, and time-major GatedDeltaNet contract.

Known limitations

• skip_dispatch_pad_tokens currently covers the standard single-context MoE forward, not the intra-layer multi-microbatch/domino-EP path.
• GatedDeltaNet currently requires B == 1, num_value_heads divisible by num_key_heads, and equal key/value head dimensions.
• In normal non-SP NPU GatedDeltaNet backward, PyTorch's generic mixed-QKV split backward produces a time-major contiguous gradient. The fixed-stride causal-convolution backward kernel therefore needs one additional layout materialization compared with the native-layout Tina prototype. The SP path does not have this mixed-QKV split. A stride-preserving custom autograd split is the intended follow-up optimization.
• Dynamic device-task and IRQ discovery is used by export_bind_config(). Trainer run() uses the packaged binding configuration; host IRQ setup remains an explicit launch-script operation.

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