[stm32h5_rcc, stm32h5_rng, stm32h5_flash, stm32h5_spi, boards] Fix small bugs. Add cortex-m33 platform header

Author: AlexLanzano

boards/stm32h563zi_nucleo/board.c

@@ -74,7 +74,7 @@ whal_Gpio g_whalGpio = {
                 .pull = WHAL_STM32H5_GPIO_PULL_NONE,
                 .altFn = 0,
             },
-            [UART_TX_PIN] = { /* USART3 TX on PD8 */
+            [UART_TX_PIN] = { /* USART2 TX on PD5 */
                 .port = WHAL_STM32H5_GPIO_PORT_D,
                 .pin = 5,
                 .mode = WHAL_STM32H5_GPIO_MODE_ALTFN,
@@ -134,10 +134,10 @@ whal_Gpio g_whalGpio = {
 
 /* Timer */
 whal_Timer g_whalTimer = {
-    WHAL_CORTEX_M4_SYSTICK_DEVICE,
+    WHAL_CORTEX_M33_SYSTICK_DEVICE,
 
     .cfg = &(whal_SysTick_Cfg) {
-        .cyclesPerTick = 168000000 / 1000, /* 250 MHz / 1 kHz = 1 ms tick */
+        .cyclesPerTick = 168000000 / 1000, /* 168 MHz / 1 kHz = 1 ms tick */
         .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK,
         .tickInt = WHAL_SYSTICK_TICKINT_ENABLED,
     },
@@ -187,20 +187,8 @@ whal_Flash g_whalFlash = {
 void Board_WaitMs(size_t ms)
 {
     uint32_t startCount = g_tick;
-    g_waiting = 1;
-    while (1) {
-        uint32_t currentCount = g_tick;
-        if (g_tickOverflow) {
-            if ((UINT32_MAX - startCount) + currentCount > ms) {
-                break;
-            }
-        } else if (currentCount - startCount > ms) {
-            break;
-        }
-    }
-
-    g_waiting = 0;
-    g_tickOverflow = 0;
+    while ((g_tick - startCount) < ms)
+        ;
 }
 
 /*

src/clock/stm32h5_rcc.c

@@ -305,7 +305,12 @@ whal_Error whal_Stm32h5RccHsi_Deinit(whal_Clock *clkDev)
 
 whal_Error whal_Stm32h5Rcc_Enable(whal_Clock *clkDev, const void *clk)
 {
-    whal_Stm32h5Rcc_Clk *stClk = (whal_Stm32h5Rcc_Clk *)clk;
+    whal_Stm32h5Rcc_Clk *stClk;
+
+    if (!clkDev || !clk)
+        return WHAL_EINVAL;
+
+    stClk = (whal_Stm32h5Rcc_Clk *)clk;
 
     whal_Reg_Update(clkDev->regmap.base, stClk->regOffset, stClk->enableMask,
                     whal_SetBits(stClk->enableMask, stClk->enablePos, 1));
@@ -315,7 +320,12 @@ whal_Error whal_Stm32h5Rcc_Enable(whal_Clock *clkDev, const void *clk)
 
 whal_Error whal_Stm32h5Rcc_Disable(whal_Clock *clkDev, const void *clk)
 {
-    whal_Stm32h5Rcc_Clk *stClk = (whal_Stm32h5Rcc_Clk *)clk;
+    whal_Stm32h5Rcc_Clk *stClk;
+
+    if (!clkDev || !clk)
+        return WHAL_EINVAL;
+
+    stClk = (whal_Stm32h5Rcc_Clk *)clk;
 
     whal_Reg_Update(clkDev->regmap.base, stClk->regOffset, stClk->enableMask,
                     whal_SetBits(stClk->enableMask, stClk->enablePos, 0));

src/flash/stm32h5_flash.c

@@ -161,7 +161,15 @@ whal_Error whal_Stm32h5Flash_Unlock(whal_Flash *flashDev, size_t addr,
 whal_Error whal_Stm32h5Flash_Read(whal_Flash *flashDev, size_t addr,
                                    uint8_t *data, size_t dataSz)
 {
-    (void)flashDev;
+    whal_Stm32h5Flash_Cfg *cfg;
+
+    if (!flashDev || !flashDev->cfg || !data)
+        return WHAL_EINVAL;
+
+    cfg = flashDev->cfg;
+
+    if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size)
+        return WHAL_EINVAL;
 
     uint8_t *flashAddr = (uint8_t *)addr;
     for (size_t i = 0; i < dataSz; ++i)
@@ -260,6 +268,9 @@ whal_Error whal_Stm32h5Flash_Erase(whal_Flash *flashDev, size_t addr,
     cfg = flashDev->cfg;
     regmap = &flashDev->regmap;
 
+    if (dataSz == 0)
+        return WHAL_SUCCESS;
+
     if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size)
         return WHAL_EINVAL;
 

src/rng/stm32h5_rng.c

@@ -57,17 +57,49 @@
 
 whal_Error whal_Stm32h5Rng_Init(whal_Rng *rngDev)
 {
+    whal_Stm32h5Rng_Cfg *cfg;
+    const whal_Regmap *reg;
+    whal_Error err;
+
     if (!rngDev || !rngDev->cfg)
         return WHAL_EINVAL;
 
-    return WHAL_SUCCESS;
+    cfg = (whal_Stm32h5Rng_Cfg *)rngDev->cfg;
+    reg = &rngDev->regmap;
+
+    /*
+     * Apply NIST-certified configuration via CONDRST sequence:
+     * 1. Write CONDRST=1 with configuration bits, RNGEN=0
+     * 2. Write HTCR magic key then HTCR value (while CONDRST=1)
+     * 3. Write NSCR value (while CONDRST=1)
+     * 4. Write CONDRST=0 with RNGEN=1 to start
+     */
+    whal_Reg_Write(reg->base, RNG_CR_REG,
+                   RNG_CR_NIST_CFG | RNG_CR_CONDRST_Msk);
+
+    whal_Reg_Write(reg->base, RNG_HTCR_REG, RNG_HTCR_MAGIC);
+    whal_Reg_Write(reg->base, RNG_HTCR_REG, RNG_HTCR_NIST_VAL);
+    whal_Reg_Write(reg->base, RNG_NSCR_REG, RNG_NSCR_NIST_VAL);
+
+    whal_Reg_Write(reg->base, RNG_CR_REG,
+                   RNG_CR_NIST_CFG | RNG_CR_RNGEN_Msk);
+
+    /* Wait for CONDRST to clear (reset complete) */
+    err = whal_Reg_ReadPoll(reg->base, RNG_CR_REG,
+                            RNG_CR_CONDRST_Msk, 0, cfg->timeout);
+
+    return err;
 }
 
 whal_Error whal_Stm32h5Rng_Deinit(whal_Rng *rngDev)
 {
     if (!rngDev || !rngDev->cfg)
         return WHAL_EINVAL;
 
+    /* Disable the RNG peripheral */
+    whal_Reg_Update(rngDev->regmap.base, RNG_CR_REG, RNG_CR_RNGEN_Msk,
+                    whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 0));
+
     return WHAL_SUCCESS;
 }
 
@@ -89,29 +121,6 @@ whal_Error whal_Stm32h5Rng_Generate(whal_Rng *rngDev, uint8_t *rngData,
     (void)(cfg);
 #endif
 
-    /*
-     * Apply NIST-certified configuration via CONDRST sequence:
-     * 1. Write CONDRST=1 with configuration bits, RNGEN=0
-     * 2. Write HTCR magic key then HTCR value (while CONDRST=1)
-     * 3. Write NSCR value (while CONDRST=1)
-     * 4. Write CONDRST=0 with RNGEN=1 to start
-     */
-    whal_Reg_Write(reg->base, RNG_CR_REG,
-                   RNG_CR_NIST_CFG | RNG_CR_CONDRST_Msk);
-
-    whal_Reg_Write(reg->base, RNG_HTCR_REG, RNG_HTCR_MAGIC);
-    whal_Reg_Write(reg->base, RNG_HTCR_REG, RNG_HTCR_NIST_VAL);
-    whal_Reg_Write(reg->base, RNG_NSCR_REG, RNG_NSCR_NIST_VAL);
-
-    whal_Reg_Write(reg->base, RNG_CR_REG,
-                   RNG_CR_NIST_CFG | RNG_CR_RNGEN_Msk);
-
-    /* Wait for CONDRST to clear (reset complete) */
-    err = whal_Reg_ReadPoll(reg->base, RNG_CR_REG,
-                            RNG_CR_CONDRST_Msk, 0, cfg->timeout);
-    if (err)
-        goto exit;
-
     while (offset < rngDataSz) {
         /* Wait for a random value to be ready */
         WHAL_TIMEOUT_START(cfg->timeout);
@@ -137,18 +146,14 @@ whal_Error whal_Stm32h5Rng_Generate(whal_Rng *rngDev, uint8_t *rngData,
         }
 
         /* Read 32-bit random value */
-        uint32_t rnd = *(volatile uint32_t *)(reg->base + RNG_DR_REG);
+        uint32_t rnd = (uint32_t)whal_Reg_Read(reg->base, RNG_DR_REG);
 
         /* Copy bytes into output buffer */
         for (size_t i = 0; i < 4 && offset < rngDataSz; i++, offset++)
             rngData[offset] = (uint8_t)(rnd >> (i * 8));
     }
 
 exit:
-    /* Disable the RNG peripheral */
-    whal_Reg_Update(reg->base, RNG_CR_REG, RNG_CR_RNGEN_Msk,
-                    whal_SetBits(RNG_CR_RNGEN_Msk, RNG_CR_RNGEN_Pos, 0));
-
     return err;
 }
 

src/spi/stm32h5_spi.c

@@ -172,7 +172,7 @@ whal_Error whal_Stm32h5Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg)
     cpol = (comCfg->mode >> 1) & 1;
     cpha = comCfg->mode & 1;
     dsize = comCfg->wordSz - 1;
-    fthlv = (comCfg->wordSz <= 8) ? 0 : 0; /* 1 data frame threshold */
+    fthlv = 0; /* 1 data frame threshold */
 
     /* Set baud rate, data size, FIFO threshold */
     whal_Reg_Update(reg->base, SPI_CFG1_REG,

wolfHAL/clock/stm32h5_rcc.h

@@ -63,7 +63,7 @@ typedef enum {
 typedef struct whal_Stm32h5Rcc_PllClkCfg {
     whal_Stm32h5Rcc_PllClockSrc clkSrc; /* PLL input source */
     uint16_t n; /* PLLN multiplier (3-512, VCO = input * (n+1)) */
-    uint8_t m;  /* PLLM divider (0-63, input / (m+1)) */
+    uint8_t m;  /* PLLM divider (1-63, input / m) */
     uint8_t p;  /* PLLP divider (0-127, output / (p+1)) */
     uint8_t q;  /* PLLQ divider (0-127, output / (q+1)) */
     uint8_t r;  /* PLLR divider (0-127, output / (r+1)) */

wolfHAL/platform/arm/cortex_m33.h

@@ -0,0 +1,13 @@
+#ifndef WHAL_CORTEX_M33_H
+#define WHAL_CORTEX_M33_H
+
+#include <wolfHAL/timer/systick.h>
+
+#define WHAL_CORTEX_M33_SYSTICK_DEVICE  \
+    .regmap = {                         \
+        .base = 0xE000E010,             \
+        .size = 0x400,                  \
+    },                                  \
+    .driver = &whal_SysTick_Driver
+
+#endif /* WHAL_CORTEX_M33_H */

wolfHAL/platform/st/stm32h563xx.h

@@ -1,7 +1,7 @@
 #ifndef WHAL_STM32H563XX_H
 #define WHAL_STM32H563XX_H
 
-#include <wolfHAL/platform/arm/cortex_m4.h>
+#include <wolfHAL/platform/arm/cortex_m33.h>
 
 #include <wolfHAL/clock/stm32h5_rcc.h>
 #include <wolfHAL/gpio/stm32h5_gpio.h>