[dv,vendor] Disable Zc* tests and revert compiler update related flags

Temporarily disable the Zcb/Zcmp tests while we wait to upgrade the
compiler. This ensures the CI can run regressions with the current
compiler to verify that we do not introduce breaking changes.

Author: SamuelRiedel

dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml

@@ -1157,36 +1157,3 @@
   rtl_test: core_ibex_base_test
   rtl_params:
     RV32B: ["ibex_pkg::RV32BFull", "ibex_pkg::RV32BOTEarlGrey", "ibex_pkg::RV32BBalanced"]
-
-- test: riscv_zcb_balanced_test
-  desc: >
-    Random instruction test with zcb instructions in balanced configuration
-  iterations: 10
-  gen_test: riscv_rand_instr_test
-  gen_opts: >
-    +enable_zcb_extension=1
-  rtl_test: core_ibex_base_test
-
-- test: riscv_zcmp_balanced_test
-  desc: >
-    Random instruction test with zcmp instructions in balanced configuration
-  iterations: 10
-  gen_test: riscv_rand_instr_test
-  gen_opts: >
-    +enable_zcb_extension=1
-    +enable_zcmp_extension=1
-  rtl_test: core_ibex_base_test
-
-- test: riscv_zcmp_directed_test
-  desc: >
-    Random instruction test with zcmp instructions in balanced configuration
-  iterations: 10
-  gen_test: riscv_instr_base_test
-  gen_opts: >
-    +enable_zcb_extension=1
-    +enable_zcmp_extension=1
-    +directed_instr_0=riscv_zcmp_chain_instr_stream,1
-    +instr_cnt=100
-    +num_of_sub_program=0
-    +no_branch_jump=1
-  rtl_test: core_ibex_base_test

dv/uvm/core_ibex/scripts/ibex_cmd.py

@@ -114,9 +114,8 @@ def get_isas_for_config(cfg: Config) -> Tuple[str, str]:
 
     has_bitmanip = cfg.rv32b != 'ibex_pkg::RV32BNone'
     toolchain_isa = base_isa + ('b' if has_bitmanip else '')
-    toolchain_isa = toolchain_isa + ('_zicsr_zifencei_zcb_zcmp')
 
-    return (toolchain_isa, '_'.join([base_isa] + ['Zicsr','Zifencei','Zcb','Zcmp'] + bitmanip_isa))
+    return (toolchain_isa, '_'.join([base_isa] + bitmanip_isa))
 
 
 _TestEntry = Dict[str, object]

dv/uvm/core_ibex/tests/core_ibex_base_test.sv

@@ -70,10 +70,6 @@ class core_ibex_base_test extends uvm_test;
     isa = {"rv32", RV32E ? "e" : "i"};
     if (RV32M != RV32MNone) isa = {isa, "m"};
     isa = {isa, "c"};
-    isa = {isa, "_Zicsr"};
-    isa = {isa, "_Zifencei"};
-    isa = {isa, "_Zcb"};
-    isa = {isa, "_Zcmp"};
     case (RV32B)
       RV32BNone:
         ;

vendor/patches/google_riscv-dv/0004-compiler-flags.patch

@@ -0,0 +1,55 @@
+--- a/run.py
++++ b/run.py
+@@ -951,40 +951,40 @@ def load_config(args, cwd):
+             args.core_setting_dir = cwd + "/target/" + args.target
+         if args.target == "rv32imc":
+             args.mabi = "ilp32"
+-            args.isa = "rv32imc_zicsr_zifencei"
++            args.isa = "rv32imc"
+         elif args.target == "rv32imafdc":
+             args.mabi = "ilp32"
+-            args.isa = "rv32imafdc_zicsr_zifencei"
++            args.isa = "rv32imafdc"
+         elif args.target == "rv32imc_sv32":
+             args.mabi = "ilp32"
+-            args.isa = "rv32imc_zicsr_zifencei"
++            args.isa = "rv32imc"
+         elif args.target == "multi_harts":
+             args.mabi = "ilp32"
+-            args.isa = "rv32gc_zicsr_zifencei"
++            args.isa = "rv32gc"
+         elif args.target == "rv32imcb":
+             args.mabi = "ilp32"
+-            args.isa = "rv32imcb_zicsr_zifencei"
++            args.isa = "rv32imcb"
+         elif args.target == "rv32i":
+             args.mabi = "ilp32"
+-            args.isa = "rv32i_zicsr_zifencei"
++            args.isa = "rv32i"
+         elif args.target == "rv64imc":
+             args.mabi = "lp64"
+-            args.isa = "rv64imc_zicsr_zifencei"
++            args.isa = "rv64imc"
+         elif args.target == "rv64imcb":
+             args.mabi = "lp64"
+-            args.isa = "rv64imcb_zicsr_zifencei"
++            args.isa = "rv64imcb"
+         elif args.target == "rv64gc":
+             args.mabi = "lp64"
+-            args.isa = "rv64gc_zicsr_zifencei"
++            args.isa = "rv64gc"
+         elif args.target == "rv64gcv":
+             args.mabi = "lp64"
+-            args.isa = "rv64gcv_zicsr_zifencei"
++            args.isa = "rv64gcv"
+         elif args.target == "ml":
+             args.mabi = "lp64"
+-            args.isa = "rv64imc_zicsr_zifencei"
++            args.isa = "rv64imc"
+         elif args.target == "rv64imafdc":
+             args.mabi = "lp64"
+-            args.isa = "rv64imafdc_zicsr_zifencei"
++            args.isa = "rv64imafdc"
+         else:
+             sys.exit("Unsupported pre-defined target: {}".format(args.target))
+     else: