diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index eeb2c9a4e8f..6a6cf58ba59 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -244,6 +244,8 @@ "nxp/imx/imxrt/imxrt1064-nxp-evk", "nxp/imx/imxrt/imxrt1021-nxp-evk", "nxp/imx/imxrt/imxrt1170-nxp-evk", + "nxp/imx/imxrt/imxrt1180-nxp-evk/cm33", + "nxp/imx/imxrt/imxrt1180-nxp-evk/cm7", "nxp/mcx/mcxn/frdm-mcxn947", "nxp/mcx/mcxn/frdm-mcxn236", "nxp/mcx/mcxc/frdm-mcxc444", diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md new file mode 100644 index 00000000000..f010af0ef6b --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/README_zh.md @@ -0,0 +1,116 @@ +# i.MX RT1180 EVK 开发板 BSP 说明 + +## 简介 + +本文档为 NXP i.MX RT1180 EVK 开发板提供的 BSP (板级支持包) 的初步说明。 + +目前支持CM33和CM7的独立编译，CM33作为主核，CM7作为从核。CM33的工程可以从External Flash直接XIP，CM7的工程可以加载到ITCM运行。 + +CM33对CM7的kick off将在后续版本中支持。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +双核i.MX RT1180采用主频达800MHz的Cortex®-M7内核和主频达240MHz的Arm Cortex-M33，同时提供一流的安全保障以及丰富的网络连接功能，包括双千兆以太网和多种工业通信接口。i.MX RT1180 MCU支持宽温度范围，适用于工业控制、电机驱动等市场。 + +## 外设支持 + +本 BSP 目前对外设仅支持UART，作为第一次push的测试，之后会逐步完善。外设支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :----------------- | :----------: | :------------------------------------| +| USB 转串口 | 暂不支持 | | +| SPI Flash | 暂不支持 | | +| 以太网 | 暂不支持 | | +| **片上外设** | **支持情况** | **备注** | +| GPIO | 暂不支持 | | +| UART | 支持 | | +| SPI | 暂不支持 | | +| I2C | 暂不支持 | | +| SDIO | 暂不支持 | | +| RTC | 暂不支持 | | +| PWM | 暂不支持 | | +| CAN | 暂不支持 | | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 、IAR 以及 GCC 工程。下面以 IAR 开发环境为例，介绍如何将系统运行起来。 + +**请注意！！！** + +在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的库，否则无法通过编译）： + +```bash +pkgs --update +``` + +生成IAR工程：scons --target=iar + +生成KEIL MDK5工程：scons --target=mdk5 + +或者直接编译GCC工程：scons -j8 + +#### 硬件连接 + +使用数据线连接开发板到 PC，打开电源开关。 + +#### 编译下载 + +双击 project.eww 文件，打开 IAR 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 CMSIS-DAP 下载程序，在通过 CMSIS-DAP 连接开发板的基础上，点击下载按钮即可下载程序到开发板 + +#### 运行结果 + +下载程序成功之后，系统会自动运行。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build May 15 2026 17:19:35 + 2006 - 2024 Copyright by RT-Thread team +``` + + +### 进阶使用 + +此 BSP 默认只开启了串口 1 的功能，如果需使用更多高级外设功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入 `menuconfig` 命令配置工程，配置好之后保存退出。 + +3. 输入 `pkgs --update` 命令更新软件包。 + +4. 输入 `scons --target=mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +暂无 + +## 联系人信息 + +维护人: diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config new file mode 100644 index 00000000000..67ad7a718e3 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/.config @@ -0,0 +1,1488 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +CONFIG_RT_USING_TINY_FFS=y +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_SECURE=y +CONFIG_ARCH_ARM_CORTEX_M33=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +CONFIG_PKG_USING_CMBACKTRACE=y +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M0_M0PLUS is not set +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M3 is not set +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M4 is not set +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M7 is not set +CONFIG_PKG_CMBACKTRACE_PLATFORM_M33=y +# CONFIG_PKG_CMBACKTRACE_PLATFORM_NOT_SELECTED is not set +CONFIG_PKG_CMBACKTRACE_DUMP_STACK=y +CONFIG_PKG_CMBACKTRACE_PRINT_ENGLISH=y +# CONFIG_PKG_CMBACKTRACE_PRINT_CHINESE is not set +# CONFIG_PKG_CMBACKTRACE_PRINT_CHINESE_UTF8 is not set +# CONFIG_CMB_USING_FAL_FLASH_LOG is not set +CONFIG_PKG_CMBACKTRACE_PATH="/packages/tools/CmBacktrace" +CONFIG_PKG_USING_CMBACKTRACE_V10401=y +# CONFIG_PKG_USING_CMBACKTRACE_V10400 is not set +# CONFIG_PKG_USING_CMBACKTRACE_V10300 is not set +# CONFIG_PKG_USING_CMBACKTRACE_V10202 is not set +# CONFIG_PKG_USING_CMBACKTRACE_V10200 is not set +# CONFIG_PKG_USING_CMBACKTRACE_LATEST_VERSION is not set +CONFIG_PKG_CMBACKTRACE_VER="v1.4.1" +CONFIG_PKG_CMBACKTRACE_VER_NUM=0x10401 +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +CONFIG_PKG_USING_NXP_IMXRT_DRIVER=y +CONFIG_PKG_NXP_IMXRT_DRIVER_PATH="/packages/peripherals/hal-sdk/nxp/nxp-imxrt-sdk" +CONFIG_PKG_USING_NXP_IMXRT_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_IMXRT1180_SERIES=y + +# +# Hardware Drivers Config +# +CONFIG_BSP_USING_QSPIFLASH=y +CONFIG_SOC_MIMXRT1189CVM8C=y +CONFIG_SOC_MIMXRT1189CVM8C_CM33=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_DMA=y +# CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_SDIO is not set +CONFIG_BSP_USING_LPUART=y +CONFIG_BSP_USING_LPUART1=y +# CONFIG_BSP_LPUART1_RX_USING_DMA is not set +# CONFIG_BSP_LPUART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_LPUART3 is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_FLEXSPI is not set +# end of On-chip Peripheral Drivers + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_FS is not set +# end of Onboard Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkSettings.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkSettings.ini new file mode 100644 index 00000000000..fb02d5216cd --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/JLinkSettings.ini @@ -0,0 +1,47 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="MIMXRT1189xxx8_M33" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x00 +[MEM_MAP] +[DYN_MEM_MAP] +NumUserRegion = 0x00 diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/Kconfig new file mode 100644 index 00000000000..f94ad65eabc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/Kconfig @@ -0,0 +1,11 @@ +mainmenu "RT-Thread Configuration" + +RTT_DIR := ../../../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../../libraries/Kconfig" +rsource "board/Kconfig" + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConscript new file mode 100644 index 00000000000..c7ef7659ece --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConstruct b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConstruct new file mode 100644 index 00000000000..644e0534ecc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/SConstruct @@ -0,0 +1,88 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("..", "packages", "nxp-imxrt-sdk-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +DefaultEnvironment(tools=[]) +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./..') +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +imxrt_library = 'MIMXRT1180' +rtconfig.BSP_LIBRARY_TYPE = imxrt_library + +# include libraries +objs.extend(SConscript(os.path.join("..", "packages/nxp-imxrt-sdk-latest", imxrt_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript new file mode 100644 index 00000000000..8f55fb0d82f --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/SConscript @@ -0,0 +1,17 @@ +import rtconfig +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +# add for startup script +if rtconfig.PLATFORM in ['gcc']: + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c new file mode 100644 index 00000000000..db33aa290d8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/applications/main.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 tyustli first version + * + */ + +#include +#include +#include +#include + +int main(void) +{ + rt_kprintf("MIMXRT1180_CM33 Hello_World\r\n"); + + while (1) + { + rt_thread_mdelay(500); + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig new file mode 100644 index 00000000000..c0d69a291d9 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/Kconfig @@ -0,0 +1,239 @@ +menu "Hardware Drivers Config" + +config BSP_USING_QSPIFLASH + bool + default n + +config SOC_MIMXRT1189CVM8C + bool + select SOC_IMXRT1180_SERIES + select BSP_USING_QSPIFLASH + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config SOC_MIMXRT1189CVM8C_CM33 + bool + default y + depends on SOC_MIMXRT1189CVM8C + select ARCH_ARM_CORTEX_M33 + select ARCH_ARM_CORTEX_SECURE + +menu "On-chip Peripheral Drivers" + + config BSP_USING_DMA + bool "Enable DMA" + default n + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + config BSP_USING_USB + bool "Enable USB" + select RT_USING_USB_HOST + default n + + if BSP_USING_USB + config BSP_USB0_HOST + bool "Enable USB0" + default n + + config BSP_USB1_HOST + bool "Enable USB1" + default n + endif + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + if BSP_USING_SDIO + config CODE_STORED_ON_SDCARD + bool "Enable Code STORED On SDCARD" + default n + help + "SD CARD work as boot devive" + endif + + menuconfig BSP_USING_LPUART + bool "Enable UART" + select RT_USING_SERIAL + default y + + if BSP_USING_LPUART + config BSP_USING_LPUART1 + bool "Enable LPUART1" + default y + + config BSP_LPUART1_RX_USING_DMA + bool "Enable LPUART1 RX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_RX_DMA_CHANNEL + depends on BSP_LPUART1_RX_USING_DMA + int "Set LPUART1 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART1_TX_USING_DMA + bool "Enable LPUART1 TX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_TX_DMA_CHANNEL + depends on BSP_LPUART1_TX_USING_DMA + int "Set LPUART1 TX DMA channel (0-32)" + default 1 + + config BSP_USING_LPUART3 + bool "Enable LPUART3" + default n + + config BSP_LPUART3_RX_USING_DMA + bool "Enable LPUART3 RX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_RX_DMA_CHANNEL + depends on BSP_LPUART3_RX_USING_DMA + int "Set LPUART3 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART3_TX_USING_DMA + bool "Enable LPUART3 TX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_TX_DMA_CHANNEL + depends on BSP_LPUART3_TX_USING_DMA + int "Set LPUART3 TX DMA channel (0-32)" + default 1 + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + select RT_USING_CAN + default n + if BSP_USING_CAN + config BSP_USING_CAN3 + bool "Enable FLEXCAN3" + default n + endif + + menuconfig BSP_USING_FLEXSPI + bool "Enable FLEXSPI" + default n + if BSP_USING_FLEXSPI + config BSP_USING_FLEXSPI1 + bool "Enable FLEXSPI1" + default n + config BSP_USING_FLEXSPI2 + bool "Enable FLEXSPI2" + default n + endif +endmenu + +menu "Onboard Peripheral Drivers" + + config BSP_USING_SDRAM + bool "Enable SDRAM" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_NETDEV + select RT_USING_LWIP + default n + + + if BSP_USING_ETH + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" + default y + + if BSP_USING_PHY + config PHY_USING_KSZ8081 + bool "i.MX RT1189EVK uses ksz8081 phy" + default y + + if PHY_USING_KSZ8081 + config PHY_KSZ8081_ADDRESS + int "Specify address of phy device" + default 2 + + config PHY_RESET_KSZ8081_PORT + int "indicate port of reset" + default 6 + + config PHY_RESET_KSZ8081_PIN + int "indicate pin of reset" + default 12 + + config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE + bool "Enable the PHY ksz8081 RMII50M mode" + depends on PHY_USING_KSZ8081 + default y + endif + endif + + if BSP_USING_PHY + config PHY_USING_RTL8211F + bool "i.MX RT1189EVK uses rtl8211f phy" + default y + + if PHY_USING_RTL8211F + config PHY_RTL8211F_ADDRESS + int "Specify address of phy device" + default 1 + + config PHY_RESET_RTL8211F_PORT + int "indicate port of reset" + default 5 + + config PHY_RESET_RTL8211F_PIN + int "indicate pin of reset" + default 14 + + endif + endif + endif + + menuconfig BSP_USING_FS + bool "Enable File System" + select RT_USING_DFS_DEVFS + select RT_USING_DFS + default n + + if BSP_USING_FS + config BSP_USING_SDCARD_FATFS + bool "Enable SDCARD (FATFS)" + select BSP_USING_SDIO + select RT_USING_DFS_ELMFAT + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.c new file mode 100644 index 00000000000..80da6cdf90d --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.c @@ -0,0 +1,839 @@ +/* + * Copyright 2022-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v13.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_misc.h" +#include "fsl_dcdc.h" +#include "fsl_pmu.h" +#include "fsl_clock.h" +#include "fsl_ele_base_api.h" + +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_FlexspiClockSafeConfig + * Description : FLEXSPI clock source safe configuration weak function. + * Called before clock source configuration. + * Note : Users need override this function to change FLEXSPI clock source to stable source when executing + * code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock source + * to a stable clock to avoid instruction/data fetch issue during clock updating. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_SetFlexspiClock + * Description : This function should be overridden if executing code on FLEXSPI memory(XIP). + * To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source. + * After the clock is changed and stable, move back to run on FLEXSPI. + * Param base : FLEXSPI peripheral base address. + * Param src : FLEXSPI clock source. + * Param divider : FLEXSPI clock divider. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : EdgeLock_SetClock + * Description : Set EdgeLock clock via safe method + * Note : It requires specific sequence to change edgelock clock source, + * otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void EdgeLock_SetClock(uint8_t mux, uint8_t div) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : DCDC_SetVoltage + * Description : Set DCDC voltage via safe method + * Note : It requires specific sequence to change DCDC voltage when GDET + * is enabled, otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage) +{ +} + + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ACMP_CLK_ROOT.outFreq, value: 240 MHz} +- {id: ADC1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: ADC2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: ARM_PLL_CLK.outFreq, value: 792 MHz} +- {id: ASRC_CLK_ROOT.outFreq, value: 240 MHz} +- {id: BUS_AON_CLK_ROOT.outFreq, value: 132 MHz} +- {id: BUS_WAKEUP_CLK_ROOT.outFreq, value: 132 MHz} +- {id: CAN1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CCM_CKO1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CCM_CKO2_CLK_ROOT.outFreq, value: 50 MHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: ECAT_CLK_ROOT.outFreq, value: 100 MHz} +- {id: ECAT_PORT0_REF_CLK.outFreq, value: 50 MHz} +- {id: ECAT_PORT1_REF_CLK.outFreq, value: 50 MHz} +- {id: EDGELOCK_CLK_ROOT.outFreq, value: 200 MHz} +- {id: ENET_REFCLK_ROOT.outFreq, value: 125 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 120 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 48 MHz} +- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2160/11 MHz} +- {id: FLEXSPI_SLV_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_CLK_ROOT.outFreq, value: 240 MHz} +- {id: GPT2_CLK_ROOT.outFreq, value: 240 MHz} +- {id: I3C1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: I3C2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C0102_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0304_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0506_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPIT3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPSPI0102_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPSPI0304_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPSPI0506_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPTMR1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPUART0102_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0304_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0506_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0708_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0910_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART1112_CLK_ROOT.outFreq, value: 24 MHz} +- {id: M33_CLK_ROOT.outFreq, value: 240 MHz} +- {id: M33_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: M7_CLK_ROOT.outFreq, value: 792 MHz} +- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: MAC0_CLK_ROOT.outFreq, value: 50 MHz} +- {id: MAC1_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC2_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC3_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC4_CLK_ROOT.outFreq, value: 50 MHz} +- {id: MIC_CLK_ROOT.outFreq, value: 80 MHz} +- {id: NETC_CLK_ROOT.outFreq, value: 240 MHz} +- {id: NETC_PORT0_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT1_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT2_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT3_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT4_REF_CLK.outFreq, value: 50 MHz} +- {id: OSC_24M.outFreq, value: 24 MHz} +- {id: OSC_32K.outFreq, value: 32.768 kHz} +- {id: OSC_RC_24M.outFreq, value: 24 MHz} +- {id: OSC_RC_400M.outFreq, value: 400 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 200 MHz} +- {id: SWO_TRACE_CLK_ROOT.outFreq, value: 80 MHz} +- {id: SYS_PLL1_CLK.outFreq, value: 1 GHz} +- {id: SYS_PLL1_DIV2_CLK.outFreq, value: 500 MHz} +- {id: SYS_PLL1_DIV5_CLK.outFreq, value: 200 MHz} +- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz} +- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz} +- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz} +- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz} +- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz} +- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz} +- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz} +- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 4320/11 MHz} +- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 2880/11 MHz} +- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 4320/11 MHz} +- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 480 MHz} +- {id: TMR_1588_CLK_ROOT.outFreq, value: 240 MHz} +- {id: TMR_1588_REF_CLK.outFreq, value: 240 MHz} +- {id: TPM2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM4_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM5_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM6_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 396 MHz} +- {id: WAKEUP_AXI_CLK_ROOT.outFreq, value: 240 MHz} +settings: +- {id: AONDomainVoltage, value: OD} +- {id: CoreClockRootsInitializationConfig, value: selectedCore} +- {id: SOCDomainVoltage, value: OD} +- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low} +- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled} +- {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '2', locked: true} +- {id: ANADIG_PLL.ARM_PLL_PREDIV.scale, value: '1', locked: true} +- {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '132', locked: true} +- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M} +- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455', locked: true} +- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'} +- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'} +- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'} +- {id: ANADIG_PLL.SYS_PLL3_PFD0_DIV.scale, value: '22'} +- {id: ANADIG_PLL.SYS_PLL3_PFD1_DIV.scale, value: '33', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD1_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD2_DIV.scale, value: '22', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD2_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '18'} +- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled} +- {id: CCM.CLOCK_ROOT0.DIV.scale, value: '1', locked: true} +- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK} +- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT10.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT10.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT11.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT11.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT12.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT12.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT13.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT13.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT14.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT14.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT15.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT15.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT16.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT16.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT17.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT17.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT18.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT18.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT19.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_OSC.OSC_RC_400M} +- {id: CCM.CLOCK_ROOT20.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT21.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT21.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD0_CLK} +- {id: CCM.CLOCK_ROOT22.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT22.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD2_CLK} +- {id: CCM.CLOCK_ROOT23.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT23.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT24.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT24.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT27.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT27.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT28.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT28.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT29.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT29.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT30.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT30.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT31.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT31.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT32.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT32.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT33.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT33.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT34.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT34.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT35.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT35.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT36.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT36.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT37.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT37.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT38.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT38.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT39.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT39.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT40.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT40.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT41.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT41.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK} +- {id: CCM.CLOCK_ROOT42.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK} +- {id: CCM.CLOCK_ROOT43.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT43.MUX.sel, value: ANADIG_PLL.SYS_PLL1_CLK} +- {id: CCM.CLOCK_ROOT44.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT44.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT45.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT45.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT46.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT46.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT47.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT47.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT48.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT48.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT49.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT49.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT5.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT5.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT50.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT50.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK} +- {id: CCM.CLOCK_ROOT51.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT51.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT52.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT52.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT53.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT53.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT54.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT54.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT55.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT55.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT65.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT65.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT66.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT66.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT67.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT67.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT69.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT69.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT7.DIV.scale, value: '240', locked: true} +- {id: CCM.CLOCK_ROOT7.MUX.sel, value: ANADIG_OSC.OSC_24M} +- {id: CCM.CLOCK_ROOT70.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT70.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT71.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT71.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT72.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT72.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT73.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT73.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK} +- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240', locked: true} +- {id: CCM.CLOCK_ROOT8.MUX.sel, value: ANADIG_OSC.OSC_24M} +- {id: CCM.CLOCK_ROOT9.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT9.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +sources: +- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT2_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT3_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT4_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.SAI1_MCLK_EXT.outFreq, value: 100 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI2_MCLK_EXT.outFreq, value: 200 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI3_MCLK_EXT.outFreq, value: 300 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI4_MCLK_EXT.outFreq, value: 400 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SPDIF_CLK_EXT.outFreq, value: 2 MHz} +- {id: BLK_CTRL_WAKEUPMIX.TMR_1588_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { + .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .loopDivider = 132, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + }; + +const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = { + .pllDiv2En = 1, /* Enable Sys Pll1 divide-by-2 clock or not */ + .pllDiv5En = 1, /* Enable Sys Pll1 divide-by-5 clock or not */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = { + .mfd = 268435455, /* Denominator of spread spectrum */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + clock_root_config_t rootCfg = {0}; + + /* Init OSC RC 400M */ + CLOCK_OSC_EnableOscRc400M(); + + /* Switch both core to OscRC400M first */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + +#if (__CORTEX_M == 33) + /* When FlexSPI2 is used, CM33 root clock must be higher than 1/4 + of FlexSPI2 root clock, so set it to OSC RC 400M(but not OSC RC 24M) + firstly as common setting */ + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + +#if (__CORTEX_M == 7) + DCDC_SetVoltage(kDCDC_CORE0, kDCDC_1P0Target1P125V); + DCDC_SetVoltage(kDCDC_CORE1, kDCDC_1P0Target1P125V); + /* FBB need to be enabled in OverDrive(OD) mode */ + PMU_EnableFBB(ANADIG_PMU, true); +#endif + + /* Config CLK_1M */ + CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); + + /* Init OSC RC 24M */ + CLOCK_OSC_EnableOscRc24M(true); + + /* Config OSC 24M */ + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); + /* Wait for 24M OSC to be stable. */ + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) + { + } + + /* Call function BOARD_FlexspiClockSafeConfig() to move FlexSPI clock to a stable clock source to avoid + instruction/data fetch issue when updating PLL if XIP(execute code on FLEXSPI memory). */ + BOARD_FlexspiClockSafeConfig(); + + /* Init Arm Pll. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + + /* Init Sys Pll1. */ + CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN); + + +#ifndef USE_SDRAM + /* Init Sys Pll2. */ + CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN); + /* Init System Pll2 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); +#endif + /* Init System Pll2 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); + /* Init System Pll2 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + /* Init System Pll2 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); + +#ifndef USE_HYPERRAM + /* Init Sys Pll3. */ + CLOCK_InitSysPll3(); +#endif + /* Init System Pll3 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 22); + /* Init System Pll3 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 33); +#ifndef USE_HYPERRAM + /* Init System Pll3 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 22); +#endif + /* Init System Pll3 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 18); + + /* Bypass Audio Pll. */ + CLOCK_SetPllBypass(kCLOCK_PllAudio, true); + /* DeInit Audio Pll. */ + CLOCK_DeinitAudioPll(); + + /* Module clock root configurations. */ + /* Configure M7 using ARM_PLL_CLK */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + + /* Configure M33 using SYS_PLL3_CLK */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + + /* Configure EDGELOCK using OSC_RC_400M */ + EdgeLock_SetClock(kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M, 2); + + /* Configure BUS_AON using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Aon, &rootCfg); + + /* Configure BUS_WAKEUP using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Wakeup, &rootCfg); + + /* Configure WAKEUP_AXI using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Wakeup_Axi, &rootCfg); + + /* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Swo_Trace, &rootCfg); + + /* Configure M33_SYSTICK using OSC_24M */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M33_Systick, &rootCfg); +#endif + + /* Configure M7_SYSTICK using OSC_24M */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + + /* Configure FLEXIO1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg); + + /* Configure FLEXIO2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); + + /* Configure LPIT3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lpit3, &rootCfg); + + /* Configure LPTIMER1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer1, &rootCfg); + + /* Configure LPTIMER2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer2, &rootCfg); + + /* Configure LPTIMER3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer3, &rootCfg); + + /* Configure TPM2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm2, &rootCfg); + + /* Configure TPM4 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm4, &rootCfg); + + /* Configure TPM5 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm5, &rootCfg); + + /* Configure TPM6 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm6, &rootCfg); + + /* Configure GPT1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); + + /* Configure GPT2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg); + + /* Configure FLEXSPI1 using SYS_PLL3_PFD0_CLK */ + BOARD_SetFlexspiClock(FLEXSPI1, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0, 3U); + + /* Configure FLEXSPI2 using SYS_PLL3_PFD2_CLK */ +#ifndef USE_HYPERRAM + BOARD_SetFlexspiClock(FLEXSPI2, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2, 2U); +#endif + + /* Configure FLEXSPI_SLV using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi_Slv, &rootCfg); + + /* Configure CAN1 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); + + /* Configure CAN2 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg); + + /* Configure CAN3 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); + + /* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0102, &rootCfg); + + /* Configure LPUART0304 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0304_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0304, &rootCfg); + + /* Configure LPUART0506 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0506_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0506, &rootCfg); + + /* Configure LPUART0708 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0708_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0708, &rootCfg); + + /* Configure LPUART0910 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0910_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0910, &rootCfg); + + /* Configure LPUART1112 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART1112_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart1112, &rootCfg); + + /* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0102, &rootCfg); + + /* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0304, &rootCfg); + + /* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg); + + /* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg); + + /* Configure LPSPI0304 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0304, &rootCfg); + + /* Configure LPSPI0506 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0506, &rootCfg); + + /* Configure I3C1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_I3C1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_I3c1, &rootCfg); + + /* Configure I3C2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_I3C2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_I3c2, &rootCfg); + + /* Configure USDHC1 using SYS_PLL2_PFD2_CLK */ + rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + + /* Configure USDHC2 using SYS_PLL2_PFD2_CLK */ + rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); + + /* Configure SEMC using SYS_PLL1_CLK */ +#ifndef USE_SDRAM + rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll1Out; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg); +#endif + + /* Configure ADC1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); + + /* Configure ADC2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg); + + /* Configure ACMP using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); + + /* Configure ECAT using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_ECAT_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Ecat, &rootCfg); + + /* Configure ENET using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_ENET_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Enet, &rootCfg); + + /* Configure TMR_1588 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_TMR_1588_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Tmr_1588, &rootCfg); + + /* Configure NETC using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_NETC_ClockRoot_MuxSysPll3Pfd3; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Netc, &rootCfg); + + /* Configure MAC0 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC0_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Mac0, &rootCfg); + + /* Configure MAC1 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC1_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac1, &rootCfg); + + /* Configure MAC2 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC2_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac2, &rootCfg); + + /* Configure MAC3 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC3_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac3, &rootCfg); + + /* Configure MAC4 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC4_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Mac4, &rootCfg); + + /* Configure SAI1 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg); + + /* Configure SAI2 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg); + + /* Configure SAI3 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg); + + /* Configure SAI4 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg); + + /* Configure SPDIF using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg); + + /* Configure ASRC using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg); + + /* Configure MIC using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg); + + /* Configure CKO1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); + + /* Configure CKO2 using SYS_PLL1_DIV5_CLK */ + rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxSysPll1Div5; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); + + /* Set SAI MCLK clock source. */ + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI2MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI3MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk1Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk2Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk3Sel, 0); + + /* Set ECAT PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK; + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK; + + /* Set NETC PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK; + + /* Set TMR 1588 Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_MASK; + +#if (__CORTEX_M == 7) + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7); +#else + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M33); +#endif +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.h new file mode 100644 index 00000000000..ae0e622606d --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/clock_config.h @@ -0,0 +1,366 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if __CORTEX_M == 7 + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */ +#else + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */ +#endif + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 240000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */ +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 80000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */ +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 80000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */ +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 240000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */ +#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */ +#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */ +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 80000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 50000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 100000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 125000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */ +#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */ +#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */ +#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */ +#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */ +#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */ +#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */ +#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */ +#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */ +#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */ +#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */ +#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */ +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 50000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 125000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 125000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 125000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 50000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 80000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */ +#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 240000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 50000000UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 50000000UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 50000000UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 50000000UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 50000000UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */ +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 0UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 0UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 0UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 0UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 0UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 0UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 0UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 0UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 0UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 200000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 0UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 1000000000UL /* Clock consumers of SYS_PLL1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 500000000UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 200000000UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 261818181UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 480000000UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 240000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 240000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */ +#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */ +#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */ +#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 396000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ +#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ + + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if __CORTEX_M == 7 + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */ +#else + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */ +#endif + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 240000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */ +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 80000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */ +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 80000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */ +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 240000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */ +#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */ +#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */ +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 80000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 50000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 100000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 125000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */ +#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */ +#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */ +#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */ +#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */ +#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */ +#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */ +#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */ +#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */ +#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */ +#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */ +#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */ +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 50000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 125000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 125000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 125000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 50000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 80000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */ +#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 240000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 50000000UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 50000000UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 50000000UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 50000000UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 50000000UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */ +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 0UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 0UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 0UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 0UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 0UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 0UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 0UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 0UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 0UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 200000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 0UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 1000000000UL /* Clock consumers of SYS_PLL1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 500000000UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 200000000UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 261818181UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 480000000UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 240000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 240000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */ +#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */ +#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */ +#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 396000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ +#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ + + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c new file mode 100644 index 00000000000..9ef62aca0ed --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.c @@ -0,0 +1,113 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v15.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 0.15.9 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "fsl_rgpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, + slew_rate: Slow} + - {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, + slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins, assigned for the Cortex-M33 core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + +// /* GPIO configuration on GPIO_AD_27 (pin M16) */ +// rgpio_pin_config_t gpio4_pinM16_config = { +// .pinDirection = kRGPIO_DigitalOutput, +// .outputLogic = 1U, +// }; +// /* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */ +// RGPIO_PinInit(RGPIO4, 27U, &gpio4_pinM16_config); + +// IOMUXC_SetPinMux( +// IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */ +// 0U); + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ +} + +void BOARD_InitLeds(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc1); /* Turn on LPCG: LPCG is ON. */ + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + + /* GPIO configuration on GPIO_AD_27 (pin M16) */ + rgpio_pin_config_t gpio4_pinM16_config = { + .pinDirection = kRGPIO_DigitalOutput, + .outputLogic = 1U, + }; + /* Initialize GPIO functionality on GPIO_AD_27 (pin M16) */ + RGPIO_PinInit(RGPIO4, 27U, &gpio4_pinM16_config); + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_27_GPIO4_IO27, /* GPIO_AD_27 is configured as GPIO4_IO27 */ + 0U); +} + + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h new file mode 100644 index 00000000000..03590a1759b --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/MCUX_Config/pin_mux.h @@ -0,0 +1,53 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */ + +void BOARD_InitLeds(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript new file mode 100644 index 00000000000..0cfbe5a55b1 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/SConscript @@ -0,0 +1,31 @@ +Import('rtconfig') + +from building import * +import rtconfig + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +MCUX_Config/clock_config.c +MCUX_Config/pin_mux.c +""") + +CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] +CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm33', 'MCUXPRESSO_SDK', 'MCUX_META_BUILD', 'MIMXRT1189_cm33_SERIES', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'XIP_EXTERNAL_FLASH=1', 'ARM_MATH_CM33'] + +if rtconfig.PLATFORM in ['gcc']: + CPPDEFINES += ['__STARTUP_INITIALIZE_RAMFUNCTION'] + +if rtconfig.PLATFORM in ['armcc', 'armclang']: + # CPPDEFINES += ['SDK_DEBUGCONSOLE'] + CPPDEFINES += ['NDEBUG'] + +if rtconfig.PLATFORM in ['iccarm']: + CPPDEFINES += ['NDEBUG'] + # CPPDEFINES += ['FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c new file mode 100644 index 00000000000..2557a72bc40 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.c @@ -0,0 +1,1284 @@ +/* + * Copyright 2021-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include "drv_uart.h" + +#include "fsl_common.h" +#include "board.h" +#if defined(SDK_NETC_USED) && SDK_NETC_USED + #include "fsl_netc_soc.h" + #include "fsl_netc_ierb.h" +#endif /* SDK_NETC_USED */ +#include "fsl_iomuxc.h" +#include "fsl_cache.h" +#include "fsl_ele_base_api.h" +#include "fsl_dcdc.h" +#include "fsl_trdc.h" +#include "fsl_rgpio.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_FLEXSPI_DLL_LOCK_RETRY (10) + +/******************************************************************************* + * Variables + ******************************************************************************/ + +AT_QUICKACCESS_SECTION_DATA(volatile uint32_t g_systickCounter); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* MPU configuration. */ +#if __CORTEX_M == 7 +void BOARD_ConfigMPU(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_aux$$Base[]; + uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; + uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); + uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; + uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; +#endif +#if defined(__USE_SHMEM) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; + /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ + extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; + uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; + uint32_t rpmsgShmemSize = ((uint32_t)Image$$RPMSG_SH_MEM_aux$$Base) - rpmsgShmemStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_SHMEM_REGION; + extern uint32_t __top_SHMEM_REGION; + uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION); + uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __RPMSG_SH_MEM_START[]; + extern uint32_t __RPMSG_SH_MEM_SIZE[]; + uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START; + uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; +#endif +#endif + volatile uint32_t i; + + /* Disable I cache and D cache */ + L1CACHE_DisableICache(); + L1CACHE_DisableDCache(); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* clang-format off */ + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outer cache + * policy, please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in mpu_armv7.h. + */ + + /* clang-format on */ + + /* + * Add default region to deny access to whole address space to workaround speculative prefetch. + * Refer to Arm errata 1013783-B for more details. + */ + + /* Region 0 setting: Instruction access disabled, No data access permission. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2GB); + + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ /*ITCM*/ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ /*DTCM*/ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + MPU->RBAR = ARM_MPU_RBAR(6, 0x20480000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM1*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB); +#else + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM1*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); +#endif + + MPU->RBAR = ARM_MPU_RBAR(7, 0x20500000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_256KB); +#else + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); +#endif + +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI1*/ + MPU->RBAR = ARM_MPU_RBAR(8, 0x28000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB); +#endif + +#if defined(USE_HYPERRAM) + MPU->RBAR = ARM_MPU_RBAR(9, 0x04000000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write through. */ /*FSPI2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_8MB); +#else + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB); +#endif +#endif + +#if defined(USE_SDRAM) + MPU->RBAR = ARM_MPU_RBAR(10, 0x80000000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 10 setting: Memory with Normal type, not shareable, outer/inner write through */ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB); +#else + /* Region 10 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); +#endif +#endif + + i = 0; + while ((nonCacheSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % nonCacheSize)); + assert(nonCacheSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 11 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(11, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } + +#if defined(__USE_SHMEM) + i = 0; + while ((rpmsgShmemSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 12 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(12, rpmsgShmemStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } +#endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enable I cache and D cache */ + L1CACHE_EnableDCache(); + L1CACHE_EnableICache(); +} +#elif __CORTEX_M == 33 +void BOARD_ConfigMPU(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_aux$$Base[]; + uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; + uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); + uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; + uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; +#endif +#if defined(__USE_SHMEM) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; + /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ + extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; + uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; + uint32_t rpmsgShmemSize = (uint32_t)Image$$RPMSG_SH_MEM_aux$$Base - rpmsgShmemStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_SHMEM_REGION; + extern uint32_t __top_SHMEM_REGION; + uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION); + uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __RPMSG_SH_MEM_START[]; + extern uint32_t __RPMSG_SH_MEM_SIZE[]; + uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START; + uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; +#endif +#endif + uint32_t i; + uint8_t attr; + + /* Disable code & system cache */ + XCACHE_DisableCache(XCACHE_PC); + XCACHE_DisableCache(XCACHE_PS); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Attr0: device. */ + ARM_MPU_SetMemAttr(0U, ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE)); + + /* Attr1: non cacheable. */ + ARM_MPU_SetMemAttr(1U, ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE)); + + /* Attr2: non transient, write through, read allocate. */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 0U, 1U, 0U); + ARM_MPU_SetMemAttr(2U, ARM_MPU_ATTR(attr, attr)); + + /* Attr3: non transient, write back, read/write allocate. */ + attr = ARM_MPU_ATTR_MEMORY_(0U, 1U, 1U, 1U); + ARM_MPU_SetMemAttr(3U, ARM_MPU_ATTR(attr, attr)); + + /* NOTE: + * 1. When memory regions overlap, the processor generates a fault if a core access hits the overlapping regions + */ + +#if defined(USE_HYPERRAM) + /* + The default attribute of the background system address map for this address space: + normal, write through, read allocate, non-shareable, read/write in privilege and non-privilege, executable + */ + + /* Region 0 (FlexSPI2, Hyperram): [0x04000000, 0x047FFFFFF, 8M] */ +#if !defined(CACHE_MODE_WRITE_THROUGH) + /* non-shareable, read/write in privilege and non-privilege, executable. Attr 3 */ + ARM_MPU_SetRegion(0U, ARM_MPU_RBAR(0x04000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x047FFFFF, 3U)); +#endif +#endif + + /* Region 1 (Code TCM): [0x0FFE0000, 0x0FFFFFFF, 128K] */ + /* non-shareable, read/write in privilege and non-privilege, executable. Attr 2 */ + ARM_MPU_SetRegion(1U, ARM_MPU_RBAR(0x0FFE0000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x0FFFFFFF, 2U)); + + /* Region 2 (System TCM): [0x20000000, 0x2001FFFF, 128K] */ + /* non-shareable, read/write in privilege and non-privilege, executable. Attr 3 */ + ARM_MPU_SetRegion(2U, ARM_MPU_RBAR(0x20000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2001FFFF, 3U)); + + /* Region 3 (CM7 I/D TCM): [0x203C0000, 0x2043FFFF, 512K] */ + /* non-shareable, read/write in privilege and non-privilege, execute-never. Attr 1 (non cacheable). */ + ARM_MPU_SetRegion(3U, ARM_MPU_RBAR(0x203C0000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x2043FFFF, 1U)); + + /* Region 4 (CM7 I/D TCM): [0x303C0000, 0x3043FFFF, 512K] */ + /* non-shareable, read/write in privilege and non-privilege, execute-never. Attr 1 (non cacheable). */ + ARM_MPU_SetRegion(4U, ARM_MPU_RBAR(0x303C0000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x3043FFFF, 1U)); + + /* + As common setting, not set this region to avoid potential overlapping setting with NCACHE(region 8) + and SHMEM(region 9) for specific build configuration, but use the default attribute of the background + system address map. + The default attribute of the background system address map for this address space: + normal, write back, write/read allocate, non-shareable, read/write in privilege and non-privilege, executable + + If application needs to fine tune MPU settings, here is an example: + // Region 11 (OCRAM1): [0x20480000, 0x204FFFFF, 512K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 3U)); + + // Region 12 (OCRAM2): [0x20500000, 0x2053FFFF, 256K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(12U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 3U)); + */ + + /* Region 5 (FlexSPI1, Nor Flash): [0x28000000, 0x28FFFFFF, 16M] */ + /* non-shareable, read only in privilege and non-privileged, executable. Attr 2 */ + ARM_MPU_SetRegion(5U, ARM_MPU_RBAR(0x28000000, ARM_MPU_SH_NON, 1U, 1U, 0U), ARM_MPU_RLAR(0x28FFFFFF, 2U)); + + /* Region 6 (Peripherals): [0x40000000, 0x7FFFFFFF, 1G ] */ + /* non-shareable, read/write in privilege and non-privileged, execute-never. Attr 0 (device). */ + ARM_MPU_SetRegion(6U, ARM_MPU_RBAR(0x40000000, ARM_MPU_SH_NON, 0U, 1U, 1U), ARM_MPU_RLAR(0x7FFFFFFF, 0U)); + +#if defined(USE_SDRAM) + /* + As common setting, not set this region to avoid potential overlapping setting with NCACHE(region 8) + and SHMEM(region 9) for specific build configuration, but use the default attribute of the background + system address map. + The default attribute of the background system address map for this address space: + normal, write through, read allocate, non-shareable, read/write in privilege and non-privilege, executable + + If application needs to fine tune MPU settings, here is an example: + // Region 7 (SEMC, SDRAM): [0x80000000, 0x81FFFFFF, 32M] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(7U, ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x81FFFFFF, 3U)); + */ +#endif + + i = 0; + while ((nonCacheSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32 */ + assert(nonCacheSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 8: non-shareable, read/write in privilege and non-privilege, executable. Attr 1(non-cacheable) */ + ARM_MPU_SetRegion(8U, ARM_MPU_RBAR(nonCacheStart, ARM_MPU_SH_NON, 0U, 1U, 0U), + ARM_MPU_RLAR(nonCacheStart + nonCacheSize - 1, 1U)); + } + +#if defined(__USE_SHMEM) + i = 0; + while ((rpmsgShmemSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 9: non-shareable, read/write in privilege and non-privilege, executable. Attr 1(non-cacheable) */ + ARM_MPU_SetRegion(9U, ARM_MPU_RBAR(rpmsgShmemStart, ARM_MPU_SH_NON, 0U, 1U, 0U), + ARM_MPU_RLAR(rpmsgShmemStart + rpmsgShmemSize - 1, 1U)); + } +#endif + +#if defined(CACHE_MODE_WRITE_THROUGH) + /* + * CM33 MPU settings can't overlay, so the common MPU settings for CM33 can't handle the + * CACHE_MODE_WRITE_THROUGH, otherwise it may conflict(overlay) with NCACHE and SHMEN. + * + * Assume the NCACHE/SHMEM region are located in OCRAM. + * This is a workaround that disable the cache of OCRAM1 and OCRAM 2, based on current link settings. + * It impacts the performance, application may fine tune MPU according to its own linkage. + */ + + // Region 8 (OCRAM1): [0x20480000, 0x204FFFFF, 512K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 1 + ARM_MPU_SetRegion(8U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 1U)); + + // Region 9 (OCRAM2): [0x20500000, 0x2053FFFF, 256K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 1 + ARM_MPU_SetRegion(9U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 1U)); +#endif + + // Region 11 (OCRAM1): [0x20480000, 0x204FFFFF, 512K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(11U, ARM_MPU_RBAR(0x20480000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x204FFFFF, 2U)); + + // Region 12 (OCRAM2): [0x20500000, 0x2053FFFF, 256K] + // non-shareable, read/write in privilege and non-privilege, executable. Attr 3 + ARM_MPU_SetRegion(12U, ARM_MPU_RBAR(0x20500000, ARM_MPU_SH_NON, 0U, 1U, 0U), ARM_MPU_RLAR(0x2053FFFF, 2U)); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enable code & system cache */ + XCACHE_EnableCache(XCACHE_PS); + XCACHE_EnableCache(XCACHE_PC); +} +#endif + +void BOARD_DeinitFlash(FLEXSPI_Type *base) +{ +#if (__CORTEX_M == 7) + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) + { + SCB_DisableICache(); + } +#endif + +#if (__CORTEX_M == 33) + if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 1U) /* disabled if enabled */ + { + /* Enable the to push all modified lines. */ + XCACHE_PC->CCR |= XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK | XCACHE_CCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0x00U) + { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + XCACHE_PC->CCR &= ~(XCACHE_CCR_PUSHW0_MASK | XCACHE_CCR_PUSHW1_MASK); + XCACHE_PC->CCR &= ~XCACHE_CCR_ENCACHE_MASK; + __ISB(); + __DSB(); + } +#endif + + /* Enable FLEXSPI module */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + + /* Wait until FLEXSPI is not busy */ + while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) + { + } + /* Disable module during the reset procedure */ + base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; +} + +void BOARD_InitFlash(FLEXSPI_Type *base) +{ + uint32_t status; + uint32_t lastStatus; + uint32_t retry; + + /* If serial root clock is >= 100 MHz, DLLEN set to 1, OVRDEN set to 0, then SLVDLYTARGET setting of 0x0 is + * recommended. */ + base->DLLCR[0] = 0x1U; + + /* Enable FLEXSPI module */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + + base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; + while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) + { + } + + /* Need to wait DLL locked if DLL enabled */ + if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK)) + { + lastStatus = base->STS2; + retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; + /* Wait slave delay line locked and slave reference delay line locked. */ + do + { + status = base->STS2; + if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) == + (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) + { + /* Locked */ + retry = 100; + break; + } + else if (status == lastStatus) + { + /* Same delay cell number in calibration */ + retry--; + } + else + { + retry = BOARD_FLEXSPI_DLL_LOCK_RETRY; + lastStatus = status; + } + } + while (retry > 0); + /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */ + for (; retry > 0U; retry--) + { + __NOP(); + } + } + +#if (__CORTEX_M == 7) + SCB_EnableICache(); +#endif + +#if (__CORTEX_M == 33) + if ((XCACHE_PC->CCR & XCACHE_CCR_ENCACHE_MASK) == 0U) + { + /* set command to invalidate all ways and write GO bit to initiate command */ + XCACHE_PC->CCR = XCACHE_CCR_INVW1_MASK | XCACHE_CCR_INVW0_MASK; + XCACHE_PC->CCR |= XCACHE_CCR_GO_MASK; + /* Wait until the command completes */ + while ((XCACHE_PC->CCR & XCACHE_CCR_GO_MASK) != 0U) + { + } + /* Enable cache */ + XCACHE_PC->CCR = XCACHE_CCR_ENCACHE_MASK; + __ISB(); + __DSB(); + } +#endif +} + +/* BOARD_SetFlexspiClock run in RAM used to configure FlexSPI clock source and divider when XIP. */ +void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider) +{ + clock_root_t root; + clock_lpcg_t lpcg; + + if (base == FLEXSPI1) + { + root = kCLOCK_Root_Flexspi1; + lpcg = kCLOCK_Flexspi1; + } + else if (base == FLEXSPI2) + { + root = kCLOCK_Root_Flexspi2; + lpcg = kCLOCK_Flexspi2; + } + else + { + return; + } + + if (((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) != CCM_CLOCK_ROOT_CONTROL_MUX(src)) || + ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) != CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1))) + { + /* Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the flash works correctly after the + FLEXSPI root clock changed as the default FLEXSPI configuration may does not work for the new root clock + frequency. */ + BOARD_DeinitFlash(base); + + /* Disable clock before changing clock source */ + CCM->LPCG[lpcg].DIRECT &= ~CCM_LPCG_DIRECT_ON_MASK; + __DSB(); + __ISB(); + while (CCM->LPCG[lpcg].STATUS0 & CCM_LPCG_STATUS0_ON_MASK) + { + } + + /* Update flexspi clock. */ + CCM->CLOCK_ROOT[root].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(src) | CCM_CLOCK_ROOT_CONTROL_DIV(divider - 1); + __DSB(); + __ISB(); + (void)CCM->CLOCK_ROOT[root].CONTROL; + + /* Enable FLEXSPI clock again */ + CCM->LPCG[lpcg].DIRECT |= CCM_LPCG_DIRECT_ON_MASK; + __DSB(); + __ISB(); + while (!(CCM->LPCG[lpcg].STATUS0 & CCM_LPCG_STATUS0_ON_MASK)) + { + } + + BOARD_InitFlash(base); + } +} + +/* This function is used to change FlexSPI clock to a stable source before clock sources(Such as PLL and Main clock) + * updating in case XIP(execute code on FLEXSPI memory.) */ +void BOARD_FlexspiClockSafeConfig(void) +{ + /* Move FLEXSPI clock source to OSC_RC_24M to avoid instruction/data fetch issue in XIP when updating PLL. */ + BOARD_SetFlexspiClock(FLEXSPI1, 0U, 1U); +} + +/* This function is used to set EdgeLock clock via safe method */ +void EdgeLock_SetClock(uint8_t mux, uint8_t div) +{ + if ((CLOCK_GetRootClockDiv(kCLOCK_Root_Edgelock) != (uint32_t)div) || + (CLOCK_GetRootClockMux(kCLOCK_Root_Edgelock) != (uint32_t)mux)) + { + status_t sts; + uint32_t ele_clk_mhz; + + clock_root_config_t rootCfg = + { + .div = div, + .mux = mux, + .clockOff = false, + }; + + do + { + sts = ELE_BaseAPI_ClockChangeStart(MU_RT_S3MUA); + } + while (sts != kStatus_Success); + + CLOCK_SetRootClock(kCLOCK_Root_Edgelock, &rootCfg); + + ele_clk_mhz = CLOCK_GetRootClockFreq(kCLOCK_Root_Edgelock) / 1000000UL; + do + { + sts = ELE_BaseAPI_ClockChangeFinish(MU_RT_S3MUA, ele_clk_mhz, 0); + } + while (sts != kStatus_Success); + } +} + +/* This function is used to set DCDC output voltage via safe method */ +void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage) +{ + /* + * When GDET is enabled, it is required to work with special ELE FW, which + * support ELE API VOLTAGE_CHANGE_START and VOLTAGE_CHANGE_FINISH, and + * DCDC voltage setting must be guarded with VOLTAGE_CHANGE_START and + * VOLTAGE_CHANGE_FINISH. + * + * For those ELE FW or ELE ROM, which doesn't support ELE API VOLTAGE_CHANGE_START + * and VOLTAGE_CHANGE_FINISH, there is no side effect to send such API command, + * since ELE just responde with ERROR and ingore the API command. + */ + ELE_BaseAPI_VoltageChangeStart(MU_RT_S3MUA); + + DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, (dcdc_core_slice_t)core, (dcdc_1P0_target_vol_t)targetVoltage); + + ELE_BaseAPI_VoltageChangeFinish(MU_RT_S3MUA); +} + +#if defined(SDK_NETC_USED) && SDK_NETC_USED +void BOARD_NETC_Init(void) +{ + /* EP and Switch port 0 use RMII interface. */ + NETC_SocSetMiiMode(kNETC_SocLinkEp0, kNETC_RmiiMode); + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort0, kNETC_RmiiMode); + + /* Switch port 1~3 use RGMII interface. */ + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort1, kNETC_RgmiiMode); + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort2, kNETC_RgmiiMode); + NETC_SocSetMiiMode(kNETC_SocLinkSwitchPort3, kNETC_RgmiiMode); + + /* Output reference clock for RMII interface. */ + NETC_SocSetRmiiRefClk(kNETC_SocLinkEp0, true); + NETC_SocSetRmiiRefClk(kNETC_SocLinkSwitchPort0, true); + + /* Unlock the IERB. It will warm reset whole NETC. */ + if (NETC_IERBUnlock() == kStatus_Success) + { + while (!NETC_IERBIsUnlockOver()) + { + } + } + + /* Set the access attribute, otherwise MSIX access will be blocked. */ + NETC_IERB->ARRAY_NUM_RC[0].RCMSIAMQR &= ~(7U << 27); + NETC_IERB->ARRAY_NUM_RC[0].RCMSIAMQR |= (1U << 27); + + /* Set PHY address in IERB to use MAC port MDIO, otherwise the access will be blocked. */ + NETC_SocSetLinkAddr(kNETC_SocLinkEp0, BOARD_EP0_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort0, BOARD_SWT_PORT0_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort1, BOARD_SWT_PORT1_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort2, BOARD_SWT_PORT2_PHY_ADDR); + NETC_SocSetLinkAddr(kNETC_SocLinkSwitchPort3, BOARD_SWT_PORT3_PHY_ADDR); + + /* Lock the IERB. */ + assert(NETC_IERBLock() == kStatus_Success); + while (!NETC_IERBIsLockOver()) + { + } +} +#endif /* SDK_NETC_USED */ + +void BOARD_RequestTRDC(bool bRequestAON, bool bRequestWakeup, bool bReqeustMega) +{ +#define ELE_TRDC_AON_ID 0x74 +#define ELE_TRDC_WAKEUP_ID 0x78 +#define ELE_TRDC_MEGA_ID 0x82 +#define ELE_CORE_CM33_ID 0x1 +#define ELE_CORE_CM7_ID 0x2 + +#if (__CORTEX_M == 33) + uint8_t ele_core_id = ELE_CORE_CM33_ID; +#elif (__CORTEX_M == 7) + uint8_t ele_core_id = ELE_CORE_CM7_ID; +#endif + + uint32_t ele_fw_sts; + + /* Get ELE FW status */ + ELE_BaseAPI_GetFwStatus(MU_RT_S3MUA, &ele_fw_sts); + + if (bRequestAON) + { + /* Release TRDC AON to current core */ + ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ele_core_id); + } + + /* + * TRDC MEGA request must be prior to TRDC WAKEUP, as TRDC MEGA access + * is controlled by the TRDC WAKEUP. + * note: + * If TRDC WAKEUP has been release to one core firstly, then it will fail + * to release TRDC MEGA to same/another core. + */ + if (bReqeustMega) + { + /* Release TRDC MEGA to current core */ + ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_MEGA_ID, ele_core_id); + } + + if (bRequestWakeup) + { + /* Release TRDC WAKEUP to current core */ + ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ele_core_id); + } +} + +void APP_CommonTrdcDACSetting(void) +{ + trdc_processor_domain_assignment_t procAssign = {.domainId = 0U, + .domainIdSelect = kTRDC_DidInput, + .pidDomainHitConfig = kTRDC_pidDomainHitNone0, + .pidMask = 0U, + .secureAttr = kTRDC_ForceSecure, + .pid = 0U, + .lock = false + }; + + trdc_non_processor_domain_assignment_t nonProcAssign = {.domainId = 0U, + .privilegeAttr = kTRDC_ForcePrivilege, + .secureAttr = kTRDC_ForceSecure, + .bypassDomainId = true, + .lock = false + }; + + /* 1. Set the MDAC Configuration in TRDC1. */ + /* Configure the access control for CM33(master 1 for TRDC1, MDAC_A1). */ + procAssign.domainId = 0x2U; + TRDC_SetProcessorDomainAssignment(TRDC1, (uint8_t)kTRDC1_MasterCM33, 0U, &procAssign); + /* Configure the access control for eDMA3(master 2 for TRDC1, MDAC_A2). */ + nonProcAssign.domainId = 0x7U; + TRDC_SetNonProcessorDomainAssignment(TRDC1, (uint8_t)kTRDC1_MasterDMA3, &nonProcAssign); + + /* 2. Set the MDAC Configuration in TRDC2. */ + /* Configure the access control for CM7 AHBP(master 0 for TRDC2, MDAC_W0). */ + procAssign.domainId = 0x4U; + TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCM7AHBP, 0U, &procAssign); + /* Configure the access control for CM7 AXI(master 1 for TRDC2, MDAC_W1). */ + TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCM7AXI, 0U, &procAssign); + /* Configure the access control for DAP AHB_AP_SYS(master 2 for TRDC2, MDAC_W2). */ + nonProcAssign.domainId = 0x9U; + TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterDAP, &nonProcAssign); + /* Configure the access control for CoreSight(master 3 for TRDC2, MDAC_W3). */ + nonProcAssign.domainId = 0x8U; + TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterCoreSight, &nonProcAssign); + /* Configure the access control for DMA4(master 4 for TRDC2, MDAC_W4). */ + nonProcAssign.domainId = 0x7U; + TRDC_SetNonProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterDMA4, &nonProcAssign); + /* Configure the access control for NETC(master 5 for TRDC2, MDAC_W5). */ + procAssign.domainId = 0xAU; + TRDC_SetProcessorDomainAssignment(TRDC2, (uint8_t)kTRDC2_MasterNETC, 0U, &procAssign); + + /* 3. Set the MDAC Configuration in TRDC3. */ + /* Configure the access control for uSDHC1(master 0 for TRDC3, MDAC_M0). */ + nonProcAssign.domainId = 0x5U; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUSDHC1, &nonProcAssign); + /* Configure the access control for uSDHC2(master 1 for TRDC3, MDAC_M1). */ + nonProcAssign.domainId = 0x6U; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUSDHC2, &nonProcAssign); + /* Configure the access control for USB(master 3 for TRDC3, MDAC_M3). */ + nonProcAssign.domainId = 0xBU; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterUsb, &nonProcAssign); + /* Configure the access control for FlexSPI_FLR(master 4 for TRDC3, MDAC_M4). */ + nonProcAssign.domainId = 0xAU; + TRDC_SetNonProcessorDomainAssignment(TRDC3, (uint8_t)kTRDC3_MasterFlexspiFlr, &nonProcAssign); +} + +static bool TRDC_IsValidDomain(TRDC_Type *trdc, uint8_t domain) +{ + bool r = true; + + if ((domain > 11) || (domain < 2) || (domain == 3)) + { + r = false; + } + return r; +} + +static bool TRDC_IsValidMbc(TRDC_Type *trdc, uint8_t mbc) +{ + bool r = false; + if (trdc == TRDC1) + { + switch (mbc) + { + case 0: /* TRDC1 MBC_A0 */ + case 1: /* TRDC1 MBC_A1 */ + r = true; + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + switch (mbc) + { + case 0: /* TRDC2 MBC_W0 */ + case 1: /* TRDC2 MBC_W1 */ + r = true; + break; + default: + break; + } + } + return r; +} + +static uint32_t TRDC_GetMbcMemNum(TRDC_Type *trdc, uint32_t mbc) +{ + uint32_t memNumber = 0U; + if (trdc == TRDC1) + { + uint8_t MemNum[2] = {3, 2}; + switch (mbc) + { + case 0: /* TRDC1 MBC_A0 AIPS1/Edgelock/GPIO1 */ + case 1: /* TRDC1 MBC_A1 CM33 Code-TCM/CM33 System-TCM */ + memNumber = MemNum[mbc]; + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + uint8_t MemNum[2] = {4, 4}; + switch (mbc) + { + case 0: /* TRDC2 MBC_A0 AIPS2/GPIO2, GPIO4, GPIO6/GPIO3, GPIO5/DAP (Debug) */ + case 1: /* TRDC2 MBC_A1 AIPS3/AHB_ISPAP/NIC_MAIN GPV/SRAMC */ + memNumber = MemNum[mbc]; + break; + default: + break; + } + } + return memNumber; +} + +static bool TRDC_IsValidMbcMem(TRDC_Type *trdc, uint8_t mbc, uint8_t mem) +{ + bool r = false; + if (trdc == TRDC1) + { + switch (mbc) + { + case 0: /* TRDC1 MBC_A0 */ + switch (mem) + { + case 0: /* TRDC1 MBC_A0 AIPS1 */ + r = true; + break; + case 1: /* TRDC1 MBC_A0 Edgelock */ + break; /* Intentional, Edgelock region not touched. */ + case 2: /* TRDC1 MBC_A0 GPIO1 */ + r = true; + break; + default: + break; + } + break; + case 1: /* TRDC1 MBC_A1 */ + switch (mem) + { + case 0: /* TRDC1 MBC_A1 CM33 Code-TCM */ + case 1: /* TRDC1 MBC_A1 CM33 System-TCM */ + r = true; + break; + default: + break; + } + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + switch (mbc) + { + case 0: /* TRDC2 MBC_W0 */ + switch (mem) + { + case 0: /* TRDC2 MBC_W0 AIPS2 */ + case 1: /* TRDC2 MBC_W0 GPIO2, GPIO4, GPIO6 */ + case 2: /* TRDC2 MBC_W0 GPIO3, GPIO5 */ + case 3: /* TRDC2 MBC_W0 DAP (Debug) */ + r = true; + break; + + default: + break; + } + break; + case 1: /* TRDC2 MBC_W1 */ + switch (mem) + { + case 0: /* TRDC2 MBC_W1 AIPS3 */ + case 1: /* TRDC2 MBC_W1 AHB_ISPAP */ + case 2: /* TRDC2 MBC_W1 NIC_MAIN GPV */ + case 3: /* TRDC2 MBC_W1 SRAMC */ + r = true; + break; + + default: + break; + } + break; + default: + break; + } + } + return r; +} + +static bool TRDC_IsValidMrc(TRDC_Type *trdc, uint8_t mrc) +{ + bool r = false; + if (trdc == TRDC1) + { + switch (mrc) + { + case 0: /* TRDC1 MRC_A0 */ + case 1: /* TRDC1 MRC_A1 */ + r = true; + break; + default: + break; + } + } + else if (trdc == TRDC2) + { + switch (mrc) + { + case 1: /* TRDC2 MRC_W1 */ + case 2: /* TRDC2 MRC_W2 */ + case 3: /* TRDC2 MRC_W3 */ + case 4: /* TRDC2 MRC_W4 */ + case 5: /* TRDC2 MRC_W5 */ + case 6: /* TRDC2 MRC_W6 */ + r = true; + break; + default: + break; + } + } + return r; +} + +static bool TRDC_GetMrcRegionAddr(TRDC_Type *trdc, uint8_t mrc, uint32_t *pStartAddr, uint32_t *pStopAddr) +{ + bool r = true; + if (trdc == TRDC1) + { + switch (mrc) + { + case 0: /* TRDC1 MRC_A0 CM33 ROM */ + *pStartAddr = 0x00000000UL; + *pStopAddr = 0x00027FFFUL; + break; + case 1: /* TRDC1 MRC_A1 FlexSPI2 */ + *pStartAddr = 0x04000000UL; + *pStopAddr = 0x07FFFFFFUL; + break; + default: + r = false; + break; + } + } + else if (trdc == TRDC2) + { + switch (mrc) + { + case 1: /* TRDC2 MRC_W1 FlexSPI1 */ + *pStartAddr = 0x28000000UL; + *pStopAddr = 0x2FFFFFFFUL; + break; + case 2: /* TRDC2 MRC_W2 CM7 I-TCM D-TCM */ + *pStartAddr = 0x203C0000UL; + *pStopAddr = 0x2043FFFFUL; + break; + case 3: /* TRDC2 MRC_W3 OCRAM1 */ + *pStartAddr = 0x20480000UL; + *pStopAddr = 0x204FFFFFUL; + break; + case 4: /* TRDC2 MRC_W4 OCRAM2 */ + *pStartAddr = 0x20500000UL; + *pStopAddr = 0x2053FFFFUL; + break; + case 5: /* TRDC2 MRC_W5 SEMC */ + *pStartAddr = 0x80000000UL; + *pStopAddr = 0x8FFFFFFFUL; + break; + case 6: /* TRDC2 MRC_W6 NETC */ + *pStartAddr = 0x60000000UL; + *pStopAddr = 0x60FFFFFFUL; + break; + default: + r = false; + break; + } + } + return r; +} + +void APP_CommonTrdcAccessControlSetting(TRDC_Type *trdc) +{ + trdc_hardware_config_t hwConfig; + trdc_memory_access_control_config_t memAccessConfig; + trdc_mbc_memory_block_config_t mbcBlockConfig; + trdc_mrc_region_descriptor_config_t mrcRegionConfig; + + TRDC_GetHardwareConfig(trdc, &hwConfig); + + /* Enable all read/write/execute access for MRC/MBC access control. */ + (void)memset(&memAccessConfig, 0, sizeof(memAccessConfig)); + memAccessConfig.nonsecureUsrX = 1U; + memAccessConfig.nonsecureUsrW = 1U; + memAccessConfig.nonsecureUsrR = 1U; + memAccessConfig.nonsecurePrivX = 1U; + memAccessConfig.nonsecurePrivW = 1U; + memAccessConfig.nonsecurePrivR = 1U; + memAccessConfig.secureUsrX = 1U; + memAccessConfig.secureUsrW = 1U; + memAccessConfig.secureUsrR = 1U; + memAccessConfig.securePrivX = 1U; + memAccessConfig.securePrivW = 1U; + memAccessConfig.securePrivR = 1U; + + for (uint32_t mrc = 0U; mrc < hwConfig.mrcNumber; mrc++) + { + if (TRDC_IsValidMrc(trdc, mrc)) + { + for (uint32_t i = 0U; i < 8U; i++) + { + TRDC_MrcSetMemoryAccessConfig(trdc, &memAccessConfig, mrc, i); + } + } + } + + for (uint32_t mbc = 0U; mbc < hwConfig.mbcNumber; mbc++) + { + if (TRDC_IsValidMbc(trdc, mbc)) + { + for (uint32_t i = 0U; i < 8U; i++) + { + TRDC_MbcSetMemoryAccessConfig(trdc, &memAccessConfig, mbc, i); + } + } + } + + memset(&mbcBlockConfig, 0, sizeof(mbcBlockConfig)); + mbcBlockConfig.nseEnable = false; + mbcBlockConfig.memoryAccessControlSelect = 0; + + memset(&mrcRegionConfig, 0, sizeof(mrcRegionConfig)); + mrcRegionConfig.memoryAccessControlSelect = 0U; + mrcRegionConfig.valid = true; + mrcRegionConfig.nseEnable = false; + mrcRegionConfig.regionIdx = 0U; + + for (uint32_t domain = 0; domain < hwConfig.domainNumber; domain++) + { + if (TRDC_IsValidDomain(trdc, domain)) + { + /* Set the configuration for MBC. */ + for (uint32_t mbc = 0U; mbc < hwConfig.mbcNumber; mbc++) + { + if (TRDC_IsValidMbc(trdc, mbc)) + { + uint32_t mem_num = TRDC_GetMbcMemNum(trdc, mbc); + for (uint32_t mem = 0; mem < mem_num; mem++) + { + if (TRDC_IsValidMbcMem(trdc, mbc, mem)) + { + trdc_slave_memory_hardware_config_t mbcHwConfig; + TRDC_GetMbcHardwareConfig(trdc, &mbcHwConfig, mbc, mem); + for (uint32_t block = 0; block < mbcHwConfig.blockNum; block++) + { + mbcBlockConfig.domainIdx = domain; + mbcBlockConfig.mbcIdx = mbc; + mbcBlockConfig.slaveMemoryIdx = mem; + mbcBlockConfig.memoryBlockIdx = block; + TRDC_MbcSetMemoryBlockConfig(trdc, &mbcBlockConfig); + } + } + } + } + } + + /* Set the configuration for MRC. */ + for (uint32_t mrc = 0U; mrc < hwConfig.mrcNumber; mrc++) + { + if (TRDC_IsValidMrc(trdc, mrc)) + { + uint32_t start_addr, end_addr; + + if (TRDC_GetMrcRegionAddr(trdc, mrc, &start_addr, &end_addr)) + { + mrcRegionConfig.startAddr = start_addr; + mrcRegionConfig.endAddr = end_addr; + mrcRegionConfig.domainIdx = domain; + mrcRegionConfig.mrcIdx = mrc; + TRDC_MrcSetRegionDescriptorConfig(trdc, &mrcRegionConfig); + } + else + { + assert(false); + } + } + } + } + } +} + +void BOARD_GrantTRDCFullPermissions(void) +{ + /* 1. Request TRDC ownership */ + BOARD_RequestTRDC(true, true, true); + + /* 2. Config DAC. */ + APP_CommonTrdcDACSetting(); + + /* 3. Enable all access control */ + APP_CommonTrdcAccessControlSetting(TRDC1); + APP_CommonTrdcAccessControlSetting(TRDC2); +} + +void BOARD_CommonSetting(void) +{ + BOARD_GrantTRDCFullPermissions(); +} + +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); + +} + +#ifdef BSP_USING_LPUART +void imxrt_uart_pins_init(void) +{ +#ifdef BSP_USING_LPUART1 + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + +#endif + +} +#endif /* BSP_USING_LPUART */ + +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +void rt_hw_board_init() +{ +// BOARD_CommonSetting(); + BOARD_ConfigMPU(); + BOARD_InitPins(); + + BOARD_InitLeds(); + BOARD_BootClockRUN(); + + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /*init uart device*/ + rt_hw_uart_init(); + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_HEAP + rt_kprintf("SystemCoreClock: %d Hz\n", SystemCoreClock); + rt_kprintf("Heap: 0x%08x - 0x%08x (Size: %d bytes)\n", + HEAP_BEGIN, HEAP_END, + (uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN); + + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +} + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h new file mode 100644 index 00000000000..46f34985b9e --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/board.h @@ -0,0 +1,191 @@ +/* + * Copyright 2021-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "pin_mux.h" +#include "fsl_common.h" +#include "fsl_rgpio.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMXRT1180-EVK" +#ifndef DEBUG_CONSOLE_UART_INDEX +#define DEBUG_CONSOLE_UART_INDEX 1 +#endif + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq() +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#ifndef BOARD_DEBUG_UART_CLK_ROOT +#define BOARD_DEBUG_UART_CLK_ROOT kCLOCK_Root_Lpuart0102 +#endif +#ifndef BOARD_DEBUG_UART_BASEADDR +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1 +#endif +#ifndef BOARD_DEBUG_UART_INSTANCE +#define BOARD_DEBUG_UART_INSTANCE 1U +#endif +#ifndef BOARD_UART_IRQ +#define BOARD_UART_IRQ LPUART1_IRQn +#endif +#ifndef BOARD_UART_IRQ_HANDLER +#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler +#endif +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE (115200U) +#endif + +/* Definitions for eRPC MU transport layer */ +#if defined(FSL_FEATURE_MU_SIDE_A) +#define MU_BASE MU1_MUA +#define MU_IRQ MU1_IRQn +#define MU_IRQ_HANDLER MU1_IRQHandler +#endif +#if defined(FSL_FEATURE_MU_SIDE_B) +#define MU_BASE MU1_MUB +#define MU_IRQ MU1_IRQn +#define MU_IRQ_HANDLER MU1_IRQHandler +#endif +#define MU_IRQ_PRIORITY (2) + +/*! @brief The USER_LED used for board */ +#define LOGIC_LED_ON (1U) +#define LOGIC_LED_OFF (0U) +#ifndef BOARD_USER_LED_GPIO +#define BOARD_USER_LED_GPIO RGPIO4 +#endif +#ifndef BOARD_USER_LED_GPIO_PIN +#define BOARD_USER_LED_GPIO_PIN (27U) +#endif + +#define USER_LED_INIT(output) \ + RGPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \ + BOARD_USER_LED_GPIO->PDDR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */ +#define USER_LED_OFF() \ + RGPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */ +#define USER_LED_ON() RGPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!*/ +#if defined(__ARMCC_VERSION) +extern int Image$$ARM_LIB_HEAP$$ZI$$Base; +extern int Image$$ARM_LIB_HEAP$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_END ((void*)&Image$$ARM_LIB_HEAP$$ZI$$Limit) +#elif defined(__ICCARM__) +#pragma section="HEAP" +#define HEAP_BEGIN (__section_begin("HEAP")) +#define HEAP_END (__section_end("HEAP")) +#elif defined(__GNUC__) +extern int __HeapBase; +extern int __HeapLimit; +#define HEAP_BEGIN ((void *)&__HeapBase) +#define HEAP_END ((void *)&__HeapLimit) +#endif + +/*! @brief The board flash size */ +#define BOARD_FLASH_SIZE (0x1000000U) + +void rt_hw_board_init(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_cm33.jlinkscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_cm33.jlinkscript new file mode 100644 index 00000000000..23137a7f748 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_cm33.jlinkscript @@ -0,0 +1,1041 @@ +__constant U32 _INDEX_AHB_AP_CORTEX_M33 = 3; +__constant U32 _AHB_ACC_32BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (2 << 0); +__constant U32 _AHB_ACC_16BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (1 << 0); // HMASTER = DEBUG, Private access, no Auto-increment, Access size: half word; +__constant U32 _ACCESS_AP = 1; +__constant U32 _CM33_CPUID = 0xD210; +__constant U32 _CM7_CPUID = 0x0C27; + +/* ROM trap address for CM33 core, after system reset */ +__constant U32 _ROM_TRAP0_ADDR = 0x10002932; +__constant U32 _ROM_TRAP1_ADDR = 0x100025D4; +__constant U32 _ROM_TRAP2_ADDR = 0x100025D4; + +__constant U32 _SRC_SRSR_ADDR = 0x44460050; +__constant U32 _SRC_SRMASK_ADDR = 0x44460018; +__constant U32 _SRC_SCR_ADDR = 0x44460010; +__constant U32 _SRC_AUTHEN_CTRL_ADDR = 0x44460004; +__constant U32 _SRC_SBMR2_ADDR = 0x44460044; +__constant U32 _BLK_M7_CFG_ADDR = 0x444F0080; + +__constant U32 _DWT_COMP0_ADDR = 0xE0001020; +__constant U32 _DWT_FUNC0_ADDR = 0xE0001028; + +__constant U32 _DCB_DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DCB_DEMCR_ADDR = 0xE000EDFC; + +__constant U32 _SCB_AIRCR_ADDR = 0xE000ED0C; + +__constant U32 _XCACHE_PC_CCR_ADDR = 0x44400000; +__constant U32 _XCACHE_PS_CCR_ADDR = 0x44400800; + +__constant U32 _CM33_MPU_CTRL_ADDR = 0xE000ED94; + +__constant U32 _SI_VER_ADDR = 0x5751804C; + +unsigned int cpuID; +unsigned int rom_trap_addr; + +static int _WriteViaCM33AP16(U32 Addr, U16 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + Data = (Data & 0xFFFF) | ((Data & 0xFFFF) << 16); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP16(U32 Addr) { + U32 r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +static int _WriteViaCM33AP32(U32 Addr, U32 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP32(U32 Addr) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +/* For Debug Start */ +__constant U32 _DCB_DCRSR_ADDR = 0xE000EDF4; +__constant U32 _DCB_DCRDR_ADDR = 0xE000EDF8; +__constant U32 _SCB_DFSR_ADDR = 0xE000ED30; + +__constant U32 _REG_R0 = 0x0; +__constant U32 _REG_R1 = 0x1; +__constant U32 _REG_R2 = 0x2; +__constant U32 _REG_R3 = 0x3; +__constant U32 _REG_R4 = 0x4; +__constant U32 _REG_R5 = 0x5; +__constant U32 _REG_R6 = 0x6; +__constant U32 _REG_R7 = 0x7; +__constant U32 _REG_R8 = 0x8; +__constant U32 _REG_R9 = 0x9; +__constant U32 _REG_R10 = 0xA; +__constant U32 _REG_R11 = 0xB; +__constant U32 _REG_R12 = 0xC; +__constant U32 _REG_SP = 0xD; +__constant U32 _REG_LR = 0xE; +__constant U32 _REG_PC = 0xF; +__constant U32 _REG_SP_main = 0x11; +__constant U32 _REG_SP_process = 0x12; +__constant U32 _REG_MSPLIM_S = 0x1C; +__constant U32 _REG_PSPLIM_S = 0x1D; +__constant U32 _REG_MSPLIM_NS = 0x1E; +__constant U32 _REG_PSPLIM_NS = 0x1F; + +static U32 _ReadCPUReg(int RegIndex) { + U32 v; + + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRSR_ADDR); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, RegIndex); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRDR_ADDR); + v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA); + return v; +} + +static U32 _ReadCPURegViaAP(int AP, int RegIndex) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (AP << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + + r = _ReadCPUReg(RegIndex); + return r; +} + +int debug = 0; + +void ShowDAPInfo(void) +{ + int r; + + if ( debug ) + { + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + r = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_CTRL); + JLINK_SYS_Report1("CM33 AP CSW = ", r); + } +} + +void DBG_ShowCM33Reg(void) +{ + int r, sp, pc; + + r = _ReadViaCM33AP32(_CM33_MPU_CTRL_ADDR); + JLINK_SYS_Report1(" CM33 MPU_CTRL = ", r); + r = _ReadViaCM33AP32(_XCACHE_PC_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PC_CCR = ", r); + r = _ReadViaCM33AP32(_XCACHE_PS_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PS_CCR = ", r); + + r = _ReadViaCM33AP32(_DWT_COMP0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_COMP0 = ", r); + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_FUNC0 = ", r); + + r = _ReadViaCM33AP32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" CM33 DFSR = ", r); + r = _ReadViaCM33AP32(_DCB_DEMCR_ADDR); + JLINK_SYS_Report1(" CM33 DEMCR = ", r); + r = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" CM33 DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_SP); + pc = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_PC); + JLINK_SYS_Report1(" CM33 PC = ", pc); + JLINK_SYS_Report1(" CM33 SP = ", sp); + } + else + { + JLINK_SYS_Report(" CM33 core is not halted!"); + } +} + +void DBG_ShowCoreReg(void) +{ + int r, sp, pc; + + r = JLINK_MEM_ReadU32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" DFSR = ", r); + r = JLINK_MEM_ReadU32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPUReg(_REG_SP); + pc = _ReadCPUReg(_REG_PC); + JLINK_SYS_Report1(" PC = ", pc); + JLINK_SYS_Report1(" SP = ", sp); + } + else + { + JLINK_SYS_Report(" Core is not halted!"); + } +} + +void DBG_ShowReg(int seq) +{ + int r; + if( debug ) + { + JLINK_SYS_Report1("Seq: ", seq); + + r = _ReadViaCM33AP32(_SRC_AUTHEN_CTRL_ADDR); + JLINK_SYS_Report1(" AUTHEN_CTRL = ", r); + r = _ReadViaCM33AP32(_SRC_SRSR_ADDR); + JLINK_SYS_Report1(" SRSR = ", r); + r = _ReadViaCM33AP32(_SRC_SRMASK_ADDR); + JLINK_SYS_Report1(" SRMASK = ", r); + r = _ReadViaCM33AP32(_SRC_SCR_ADDR); + JLINK_SYS_Report1(" SCR = ", r); + r = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + JLINK_SYS_Report1(" M7_CFG = ", r); + + if(cpuID == _CM7_CPUID) + { + if((r & 0x10) == 0) + { + DBG_ShowCoreReg(); + } + + } + + DBG_ShowCM33Reg(); + } +} +/* For Debug End */ + +void _FLEXSPI1_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI1_WaitBusIdle() +{ + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FLEXSPI1_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + MEM_WriteU32(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode for JLink + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + MEM_WriteU32(0x42A1023C, 0x17); + MEM_WriteU32(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + MEM_WriteU32(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + MEM_WriteU32(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + MEM_WriteU32(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + MEM_WriteU32(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + MEM_WriteU32(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + MEM_WriteU32(0x42A10254, 0x17); +} + +void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + MEM_WriteU32(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + MEM_WriteU32(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + MEM_WriteU32(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + MEM_WriteU32(0x425E0060, 0x00004000); + + + //FLEXSPI1->FLSHCR4 = 0xC3; + MEM_WriteU32(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + MEM_WriteU32(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + MEM_WriteU32(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + MEM_WriteU32(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + MEM_WriteU32(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + MEM_WriteU32(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + MEM_WriteU32(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + MEM_WriteU32(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + MEM_WriteU32(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + MEM_WriteU32(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + MEM_WriteU32(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + MEM_WriteU32(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + MEM_WriteU32(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + MEM_WriteU32(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + MEM_WriteU32(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + MEM_WriteU32(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + MEM_WriteU32(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + MEM_WriteU32(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + MEM_WriteU32(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + MEM_WriteU32(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + MEM_WriteU32(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + MEM_WriteU32(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + MEM_WriteU32(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + MEM_WriteU32(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + MEM_WriteU32(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + MEM_WriteU32(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + MEM_WriteU32(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + MEM_WriteU32(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + MEM_WriteU32(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + MEM_WriteU32(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + MEM_WriteU32(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + MEM_WriteU32(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + MEM_WriteU32(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + MEM_WriteU32(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + MEM_WriteU32(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + MEM_WriteU32(0x425E001C, 0x01); +} + +void _FLEXSPI2_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI2_WaitBusIdle() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FlexSPI2_SetPinForOctalMode() +{ + // Config IOMUX for FlexSPI2 + MEM_WriteU32(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + MEM_WriteU32(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + MEM_WriteU32(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +void _FLEXSPI2_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + MEM_WriteU32(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +void _FLEXSPI2_ModuleInit() +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0004, 0xFFFFFFFF); // MCR1 + MEM_WriteU32(0x445E0008, 0x200001F7); // MCR2 + MEM_WriteU32(0x445E000C, 0x00000078); // AHBCR prefetch enable + MEM_WriteU32(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + MEM_WriteU32(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + MEM_WriteU32(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + MEM_WriteU32(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + MEM_WriteU32(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + MEM_WriteU32(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + MEM_WriteU32(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + MEM_WriteU32(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + MEM_WriteU32(0x445E00B8, 0x00000000); // IPRXFCR + MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR + + MEM_WriteU32(0x445E0060, 0x00000000); // FLASHA1CR0 + MEM_WriteU32(0x445E0064, 0x00000000); // FLASHA2CR0 + MEM_WriteU32(0x445E0068, 0x00000000); // FLASHB1CR0 + MEM_WriteU32(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0060, 0x00002000); // FLASHA1CR0 + MEM_WriteU32(0x445E0070, 0x00021C63); // FLASHA1CR1 + MEM_WriteU32(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E00C0, 0x00000079); // DLLCRA + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = MEM_ReadU32(0x445E00E8); + } while (0x3 != (reg & 0x3)); + JLINK_SYS_Sleep(1); + // __delay(100);//100us + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0094, 0x000000C2); // FLASHCR4 + MEM_WriteU32(0x445E0094, 0x000000C6); // FLASHCR4 + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000002); // LUTCR + MEM_WriteU32(0x445E0200, 0x8B1887A0); // LUT[0] + MEM_WriteU32(0x445E0204, 0xB7078F10); // LUT[1] + MEM_WriteU32(0x445E0208, 0x0000A704); // LUT[2] + MEM_WriteU32(0x445E020C, 0x00000000); // LUT[3] + MEM_WriteU32(0x445E0210, 0x8B188720); // LUT[4] + MEM_WriteU32(0x445E0214, 0xB7078F10); // LUT[5] + MEM_WriteU32(0x445E0218, 0x0000A304); // LUT[6] + MEM_WriteU32(0x445E021C, 0x00000000); // LUT[7] + MEM_WriteU32(0x445E0220, 0x8B1887E0); // LUT[8] + MEM_WriteU32(0x445E0224, 0xB7078F10); // LUT[9] + MEM_WriteU32(0x445E0228, 0x0000A704); // LUT[10] + MEM_WriteU32(0x445E022C, 0x00000000); // LUT[11] + MEM_WriteU32(0x445E0230, 0x8B188760); // LUT[12] + MEM_WriteU32(0x445E0234, 0xA3028F10); // LUT[13] + MEM_WriteU32(0x445E0238, 0x00000000); // LUT[14] + MEM_WriteU32(0x445E023C, 0x00000000); // LUT[15] + MEM_WriteU32(0x445E0240, 0x00000000); // LUT[16] + MEM_WriteU32(0x445E0244, 0x00000000); // LUT[17] + MEM_WriteU32(0x445E0248, 0x00000000); // LUT[18] + MEM_WriteU32(0x445E024C, 0x00000000); // LUT[19] + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + MEM_WriteU32(0x445E00A0, 0x00001000); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + MEM_WriteU32(0x445E00A0, 0x00001002); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +void CM7_InitTCM(U32 targetAddr, U32 size) { + U32 reg; + + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + + if((reg & 0x80000000) != 0) + { + // DMA channel is active, wait it get finished + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + } + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag + + _WriteViaCM33AP32(0x5201002C, 0x00000000); // DMA4->TCD[0].SLAST_SGA + _WriteViaCM33AP32(0x52010038, 0x00000000); // DMA4->TCD[0].DLAST_SGA + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR + + _WriteViaCM33AP32(0x52010020, 0x20484000); // DMA4->TCD[0].SADDR + _WriteViaCM33AP32(0x52010030, targetAddr); // DMA4->TCD[0].DADDR + _WriteViaCM33AP32(0x52010028, size); // DMA4->TCD[0].NBYTES_MLOFFNO + _WriteViaCM33AP16(0x52010036, 0x1); // DMA4->TCD[0].ELINKNO + _WriteViaCM33AP16(0x5201003E, 0x1); // DMA4->TCD[0].BITER_ELINKNO + _WriteViaCM33AP16(0x52010026, 0x0303); // DMA4->TCD[0].ATTR + _WriteViaCM33AP16(0x52010024, 0x0); // DMA4->TCD[0].SOFF + _WriteViaCM33AP16(0x52010034, 0x8); // DMA4->TCD[0].DOFF + _WriteViaCM33AP32(0x52010000, 0x7); // DMA4->TDC[0].CH_CSR + _WriteViaCM33AP16(0x5201003C, 0x8); // DMA4->TCD[0].CSR + _WriteViaCM33AP16(0x5201003C, 0x9); // DMA4->TCD[0].CSR + + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag +} + +void CM7_KickOff(int ecc_init) +{ + U32 reg, resp1, resp2; + + reg = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + if((reg & 0x10) == 0) + { + JLINK_SYS_Report("CM7 is running already"); + } + else + { + JLINK_SYS_Report("************* Begin Operations to Enable CM7 ***********************"); + + // Clock Preparation + JLINK_SYS_Report("******** Prepare Clock *********"); + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + _WriteViaCM33AP32(0x54450000, 0x100); // CLOCK_ROOT[0].CONTROL, CM7 + + // Release CM7 + _WriteViaCM33AP32(_SRC_SCR_ADDR, 0x1); + + if (ecc_init) + { + // DMA initialization + JLINK_SYS_Report("******** DMA operation *********"); + CM7_InitTCM(0x303C0000, 0x40000); + CM7_InitTCM(0x30400000, 0x40000); + } + + // Making Landing Zone + JLINK_SYS_Report("******** Creating Landing Zone *********"); + _WriteViaCM33AP32(0x303C0000, 0x20020000); + _WriteViaCM33AP32(0x303C0004, 0x00000009); + _WriteViaCM33AP32(0x303C0008, 0xE7FEE7FE); + + // VTOR 0x00 + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0010); + + // Trigger ELE + JLINK_SYS_Report("******** ELE Trigger *********"); + _WriteViaCM33AP32(0x57540200, 0x17d20106); // MU_RT_S3MUA->TR[0] + resp1 = _ReadViaCM33AP32(0x57540280); // MU_RT_S3MUA->RR[0] + resp2 = _ReadViaCM33AP32(0x57540284); // MU_RT_S3MUA->RR[1] + JLINK_SYS_Report1("ELE RESP1 : ", resp1); + JLINK_SYS_Report1("ELE RESP2 : ", resp2); + + // Deassert CM7 Wait + JLINK_SYS_Report("******** Kickoff CM7 *********"); + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0); + } +} + +void DAP_Init(void) +{ + JLINK_CORESIGHT_Configure(""); + + CORESIGHT_AddAP(0, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(1, CORESIGHT_APB_AP); + CORESIGHT_AddAP(2, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(3, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(4, CORESIGHT_APB_AP); + CORESIGHT_AddAP(5, CORESIGHT_APB_AP); + CORESIGHT_AddAP(6, CORESIGHT_APB_AP); + + JLINK_SYS_Report("***************************************************"); + if(cpuID == _CM7_CPUID) + { + CPU = CORTEX_M7; + CORESIGHT_IndexAHBAPToUse = 2; + JLINK_SYS_Report("Current core is CM7"); + } + else if(cpuID == _CM33_CPUID) + { + CPU = CORTEX_M33; + CORESIGHT_IndexAHBAPToUse = 3; + JLINK_SYS_Report("Current core is CM33"); + + ShowDAPInfo(); + CORESIGHT_AHBAPCSWDefaultSettings = (1<<29)|(1<<25)|(1<<24); + } + else + { + JLINK_SYS_Report1("Wrong CPU ID: ", cpuID); + } + JLINK_SYS_Report("***************************************************"); +} + +void CM33_Halt(void) +{ + U32 reg; + + reg = (_ReadViaCM33AP32(_SRC_SBMR2_ADDR) >> 24) & 0x3F; + + if((reg == 8) || (reg == 9)) // Serial Download Mode, or Boot From Fuse + { + JLINK_SYS_Report("Not flash execution mode, check if CM33 is halted..."); + + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + + if(0 == (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is not halted, trying to halt it. CM33 DHCSR: ", reg); + + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0001); // Enable CM33 debug control + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Halt CM33 + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + if(0 != (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is halted now. CM33 DHCSR: ", reg); + } + else + { + JLINK_SYS_Report1("CM33 still running, halt failed. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report1("CM33 is halted. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report("Flash execution mode, leave CM33 run status as it was..."); + } +} + +void Flash_Init() { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init Flash"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void HyperRAM_Init() +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init HyperRAM"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void CM33_ClearNVIC(void) { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Clear NVIC"); + JLINK_SYS_Report("***************************************************"); + JLINK_MEM_Fill(0xE000E180, 0x40, 0xFF); + JLINK_MEM_Fill(0xE000E280, 0x40, 0xFF); +} + +int InitTarget(void) +{ + int r; + cpuID = _CM33_CPUID; + + DAP_Init(); + + if(cpuID == _CM7_CPUID) + { + CM33_Halt(); + CM7_KickOff(1); + + /* Avoid to access TPIU to prevent soc hang */ + JLINK_ExecCommand("map region 0xE0040000-0xE0040FFF X"); // Mark region as illegal + } + + r = _ReadViaCM33AP32(_SI_VER_ADDR) & 0xF; + + if ( r == 1 ) + { + rom_trap_addr = _ROM_TRAP1_ADDR; + } + else if ( r == 2 ) + { + rom_trap_addr = _ROM_TRAP2_ADDR; + } + else + { + rom_trap_addr = _ROM_TRAP0_ADDR; + } + JLINK_SYS_Report1("SI_VER = ", r); + JLINK_SYS_Report1("TRAP = ", rom_trap_addr); + + return 0; +} + +int SetupTarget(void) +{ + return 0; +} + +void ResetTarget_CM33(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + + core_reset_request_bit_mask = 0x100; /* for CM33 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM33 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM33 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + ShowDAPInfo(); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + JLINK_SYS_Report("Set CM33 watch point"); + comp = JLINK_MEM_ReadU32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later */ + func = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, rom_trap_addr); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, 0x00000412); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped!"); + } + + DBG_ShowReg(4); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM33 watch point"); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, comp); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM33 is not halted after reset!"); + } +} + +void ResetTarget_CM7(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + int mem_0, mem_1, mem_2; + + core_reset_request_bit_mask = 0x400; /* for CM7 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM7 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM7 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + /* CM7_KickOff will use the first 3 words(32bits) of CM7 ITCM, save and restore them later */ + mem_0 = JLINK_MEM_ReadU32(0); + mem_1 = JLINK_MEM_ReadU32(4); + mem_2 = JLINK_MEM_ReadU32(8); + + JLINK_SYS_Report("Set CM33 watch point"); + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Enable Debug and halt CM33 core + comp = _ReadViaCM33AP32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later after reset */ + func = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + _WriteViaCM33AP32(_DCB_DEMCR_ADDR, 0x01000000); // Enable DWT of CM33 core + _WriteViaCM33AP32(_DWT_COMP0_ADDR, rom_trap_addr); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, 0x00000412); + + DBG_ShowReg(4); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped after reset!"); + } + + DBG_ShowReg(5); + + CM7_KickOff(0); + + // Halt CM7 core + JLINK_MEM_WriteU32(_DCB_DHCSR_ADDR, 0xA05F0003); + + DBG_ShowReg(6); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM7 ITCM"); + + JLINK_MEM_WriteU32(0, mem_0); + JLINK_MEM_WriteU32(4, mem_1); + JLINK_MEM_WriteU32(8, mem_2); + + JLINK_SYS_Report("restore CM33 watch points"); + _WriteViaCM33AP32(_DWT_COMP0_ADDR, comp); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM7 core can not be halted!"); + } +} + +void ResetTarget(void) { + if(cpuID == _CM7_CPUID) + { + ResetTarget_CM7(); + } + else if(cpuID == _CM33_CPUID) + { + ResetTarget_CM33(); + } +} + +int AfterResetTarget(void) +{ + U32 reg; + + if(cpuID == _CM33_CPUID) + { + // CM33 NVIC may be enabled by ROM after reset + CM33_ClearNVIC(); + } + + Flash_Init(); + HyperRAM_Init(); + + return 0; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_flexspi_nor_cm33.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_flexspi_nor_cm33.ini new file mode 100644 index 00000000000..993fb2be1ea --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/evkmimxrt1180_flexspi_nor_cm33.ini @@ -0,0 +1,417 @@ +/* + * Copyright 2023-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void _FLEXSPI1_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI1_WaitBusIdle(void) +{ + unsigned int reg; + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FLEXSPI1_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + _WDWORD(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +FUNC void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + _WDWORD(0x42A1023C, 0x17); + _WDWORD(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + _WDWORD(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + _WDWORD(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + _WDWORD(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + _WDWORD(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + _WDWORD(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + _WDWORD(0x42A10254, 0x17); +} + +FUNC void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + _WDWORD(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + _WDWORD(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + _WDWORD(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + _WDWORD(0x425E0060, 0x00004000); + + //FLEXSPI1->FLSHCR4 = 0xC3; + _WDWORD(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + _WDWORD(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + _WDWORD(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + _WDWORD(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + _WDWORD(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + _WDWORD(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + _WDWORD(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + _WDWORD(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + _WDWORD(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + _WDWORD(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + _WDWORD(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + _WDWORD(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + _WDWORD(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + _WDWORD(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + _WDWORD(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + _WDWORD(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + _WDWORD(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + _WDWORD(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + _WDWORD(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + _WDWORD(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + _WDWORD(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + _WDWORD(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + _WDWORD(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + _WDWORD(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + _WDWORD(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + _WDWORD(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + _WDWORD(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + _WDWORD(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + _WDWORD(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + _WDWORD(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + _WDWORD(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + _WDWORD(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + _WDWORD(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + _WDWORD(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + _WDWORD(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + _WDWORD(0x425E001C, 0x01); +} + +FUNC void _FLEXSPI2_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI2_WaitBusIdle(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FlexSPI2_SetPinForOctalMode(void) +{ + // Config IOMUX for FlexSPI2 + _WDWORD(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + _WDWORD(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + _WDWORD(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + _WDWORD(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + _WDWORD(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + _WDWORD(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +FUNC void _FLEXSPI2_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + _WDWORD(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +FUNC void _FLEXSPI2_ModuleInit(void) +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0004, 0xFFFFFFFF); // MCR1 + _WDWORD(0x445E0008, 0x200001F7); // MCR2 + _WDWORD(0x445E000C, 0x00000078); // AHBCR prefetch enable + _WDWORD(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + _WDWORD(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + _WDWORD(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + _WDWORD(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + _WDWORD(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + _WDWORD(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + _WDWORD(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + _WDWORD(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + _WDWORD(0x445E00B8, 0x00000000); // IPRXFCR + _WDWORD(0x445E00BC, 0x00000000); // IPTXFCR + + _WDWORD(0x445E0060, 0x00000000); // FLASHA1CR0 + _WDWORD(0x445E0064, 0x00000000); // FLASHA2CR0 + _WDWORD(0x445E0068, 0x00000000); // FLASHB1CR0 + _WDWORD(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0060, 0x00002000); // FLASHA1CR0 + _WDWORD(0x445E0070, 0x00021C63); // FLASHA1CR1 + _WDWORD(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E00C0, 0x00000079); // DLLCRA + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = _RDWORD(0x445E00E8); + } while (0x3 != (reg & 0x3)); + _Sleep_(1); + // __delay(100);//100us + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0094, 0x000000C2); // FLASHCR4 + _WDWORD(0x445E0094, 0x000000C6); // FLASHCR4 + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000002); // LUTCR + _WDWORD(0x445E0200, 0x8B1887A0); // LUT[0] + _WDWORD(0x445E0204, 0xB7078F10); // LUT[1] + _WDWORD(0x445E0208, 0x0000A704); // LUT[2] + _WDWORD(0x445E020C, 0x00000000); // LUT[3] + _WDWORD(0x445E0210, 0x8B188720); // LUT[4] + _WDWORD(0x445E0214, 0xB7078F10); // LUT[5] + _WDWORD(0x445E0218, 0x0000A304); // LUT[6] + _WDWORD(0x445E021C, 0x00000000); // LUT[7] + _WDWORD(0x445E0220, 0x8B1887E0); // LUT[8] + _WDWORD(0x445E0224, 0xB7078F10); // LUT[9] + _WDWORD(0x445E0228, 0x0000A704); // LUT[10] + _WDWORD(0x445E022C, 0x00000000); // LUT[11] + _WDWORD(0x445E0230, 0x8B188760); // LUT[12] + _WDWORD(0x445E0234, 0xA3028F10); // LUT[13] + _WDWORD(0x445E0238, 0x00000000); // LUT[14] + _WDWORD(0x445E023C, 0x00000000); // LUT[15] + _WDWORD(0x445E0240, 0x00000000); // LUT[16] + _WDWORD(0x445E0244, 0x00000000); // LUT[17] + _WDWORD(0x445E0248, 0x00000000); // LUT[18] + _WDWORD(0x445E024C, 0x00000000); // LUT[19] + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + _WDWORD(0x445E00A0, 0x00001000); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + _WDWORD(0x445E00A0, 0x00001002); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +FUNC void Flash_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init Flash\r\n"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void HyperRAM_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init HyperRAM\r\n"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void ClearNVIC(void) { + printf("***************************************************\r\n"); + printf("Clear NVIC\r\n"); + printf("***************************************************\r\n"); + memset(0xE000E180, 0x40, 0xFF); + memset(0xE000E280, 0x40, 0xFF); +} + +FUNC void Setup_PC_SP(void) +{ + SP = _RDWORD(0x2800B000); // Setup Stack Pointer + PC = _RDWORD(0x2800B004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x2800B000); // Setup Vector Table Offset Register +} + +FUNC void Setup (void) { + ClearNVIC(); + Flash_Init(); + HyperRAM_Init(); + Setup_PC_SP(); +} + +FUNC void OnResetExec (void) +{ + // executes upon RESET + Setup(); +} + +// Disable the software breakpoint for nor flash memory region +SBC 0x28000000, 0x28FFFFFF, 0 + +Setup(); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.icf new file mode 100644 index 00000000000..9dc0fc389dc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.icf @@ -0,0 +1,183 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ + +define symbol m_code_tcm_start = 0x0FFE0000; +define symbol m_code_tcm_size = 0x00020000; + +define symbol m_system_tcm_start = 0x20000000; +define symbol m_system_tcm_size = 0x00020000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +define symbol m_sdram_start = isdefinedsymbol(__dual_image__) ? 0x81E00000 : 0x80000000; +define symbol m_sdram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x02000000; +define symbol m_hyperram_start = isdefinedsymbol(__dual_image__) ? 0x04600000 : 0x04000000; +define symbol m_hyperram_size = isdefinedsymbol(__dual_image__) ? 0x00200000 : 0x00800000; +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x00800000; + +define symbol m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +define symbol m_fcb_offset = 0x400; +define symbol m_fcb_size = 0x200; +define symbol m_fcb_start = m_flash_start + m_fcb_offset; +define symbol m_fcb_end = m_fcb_start + m_fcb_size - 1; + +define symbol m_xmcd_offset = 0x800; +define symbol m_xmcd_size = 0x400; +define symbol m_xmcd_start = m_flash_start + m_xmcd_offset; +define symbol m_xmcd_end = m_xmcd_start + m_xmcd_size - 1; + +define symbol m_container_offset = 0x1000; +define symbol m_container_size = 0x2000; +define symbol m_container_start = m_flash_start + m_container_offset; +define symbol m_container_end = m_container_start + m_container_size - 1; + +define symbol app_image_offset = 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x01000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x04000; +} + +define symbol m_qacode_start = m_code_tcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +define symbol m_qadata_start = m_system_tcm_start; +define symbol m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +define symbol m_ram_vector_table_start = m_code_tcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_flash_size - app_image_offset; +define symbol m_data_size = m_system_tcm_size; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : 0; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0; + +define symbol m_text_start = m_flash_start + app_image_offset; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_system_tcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Region definition */ +define memory mem with size = 4G; +define region FCB_region = mem:[from m_fcb_start to m_fcb_end]; +define region XMCD_region = mem:[from m_xmcd_start to m_xmcd_end]; +define region CONTAINER_region = mem:[from m_container_start to m_container_end]; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +define exported symbol __CONTAINER_IMG_OFFSET = start(TEXT_region) - start(CONTAINER_region); +define exported symbol __CONTAINER_IMG_LOAD_ADDR = start(TEXT_region); +define exported symbol __CONTAINER_IMG_ENTRY_ADDR = start(TEXT_region); +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block CORE1_IMAGE_BLOCK with alignment = 16, maximum size = m_core1_image_maximum_size { section __core1_image }; + +define block RO with fixed order { readonly section .intvec, readonly, block CORE1_IMAGE_BLOCK }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess, section CodeQuickAccess }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +keep{ section .boot_hdr.conf, section .boot_hdr.xmcd_data, section .boot_hdr.container }; + +place in FCB_region { section .boot_hdr.conf }; +place in XMCD_region { section .boot_hdr.xmcd_data }; +place in CONTAINER_region { section .boot_hdr.container }; +place in TEXT_region { first block RO }; +place in QACODE_region { section .textrw, block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.lds b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.lds new file mode 100644 index 00000000000..890bc3f5764 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.lds @@ -0,0 +1,376 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189XVM8B_cm33 +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1180RM, Rev 2, 12/2022 +** Version: rev. 0.1, 2021-03-09 +** Build: b240109 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Board memory map */ +m_code_tcm_start = 0x0FFE0000; +m_code_tcm_size = 0x00020000; +m_system_tcm_start = 0x20000000; +m_system_tcm_size = 0x00020000; +m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +m_ocram1_size = 0x0007C000; +m_ocram2_start = 0x20500000; +m_ocram2_size = 0x00040000; + +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +m_sdram_start = DEFINED(__dual_image__) ? 0x81E00000 : 0x80000000; +m_sdram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x02000000; +m_hyperram_start = DEFINED(__dual_image__) ? 0x04600000 : 0x04000000; +m_hyperram_size = DEFINED(__dual_image__) ? 0x00200000 : 0x00800000; +m_flash_start = 0x28000000; +m_flash_size = 0x01000000; + +m_core1_image_maximum_size = 0x00040000; + +/* General definition */ +m_fcb_offset = 0x400; +m_fcb_size = 0x200; +m_xmcd_offset = 0x800; +m_xmcd_size = 0x400; +m_container_offset = 0x1000; +m_container_size = 0x2000; + +m_fcb_start = m_flash_start + m_fcb_offset; +m_fcb_end = m_fcb_start + m_fcb_size - 1; +m_xmcd_start = m_flash_start + m_xmcd_offset; +m_xmcd_end = m_xmcd_start + m_xmcd_size - 1; +m_container_start = m_flash_start + m_container_offset; +m_container_end = m_container_start + m_container_size - 1; + +app_image_offset = DEFINED(__dual_image__) ? 0x0010B000 : 0x0000B000; +vector_table_size = 0x00000400; +m_qacode_start = m_code_tcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); +m_qacode_end = m_code_tcm_start + m_code_tcm_size - 1; +m_qadata_start = m_system_tcm_start; +m_qadata_end = m_system_tcm_start + m_system_tcm_size - 1; +m_ram_vector_table_start = m_code_tcm_start; +m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x4000; + +/* Target specific definition, code & data allocation */ +m_code_size = m_flash_size - app_image_offset - vector_table_size; +m_data_size = m_system_tcm_size; +m_ncache_size = DEFINED(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +m_ocram1_size_for_cm7 = DEFINED(__multicore__) ? 0x40000 : 0; + +m_ram_vector_table_size = DEFINED(__ram_vector_table__) ? vector_table_size : 0; + +m_interrupts_start = m_flash_start + app_image_offset; +m_interrupts_end = m_interrupts_start + vector_table_size - 1; + +m_text_start = m_interrupts_end + 1; +m_text_end = m_text_start + m_code_size - 1; + +m_data_start = m_system_tcm_start; +m_data_end = m_data_start + m_data_size - 1; + +m_ncache_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size; +m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0); + +m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram1_start; +m_heap_end = m_heap_start + m_heap_size - 1; + +m_rpmsg_sh_mem_start = m_ocram2_start; +m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; + +/* Exported symbol definition */ +__VECTOR_TABLE = m_interrupts_start; +__VECTOR_RAM = m_ram_vector_table_start; +__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size; +__CONTAINER_IMG_OFFSET = m_interrupts_start - m_container_start; + +__NCACHE_REGION_START = m_ncache_start; +__NCACHE_REGION_SIZE = m_ncache_size; +__RPMSG_SH_MEM_START = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_start : 0; +__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_fcb_data (RX) : ORIGIN = m_fcb_start, LENGTH = m_fcb_end - m_fcb_start + 1 + m_xmcd_data (RX) : ORIGIN = m_xmcd_start, LENGTH = m_xmcd_end - m_xmcd_start + 1 + m_container_data (RX) : ORIGIN = m_container_start, LENGTH = m_container_end - m_container_start + 1 + m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES + m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = m_interrupts_end - m_interrupts_start + 1 + m_text (RX) : ORIGIN = m_text_start, LENGTH = m_text_end - m_text_start + 1 + m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_end - m_data_start + 1 + m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1 + m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_end - m_heap_start + 1 + m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1 + m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1 + m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 +} + +/* Define output sections */ +SECTIONS +{ + .fcb : + { + KEEP(*(.boot_hdr.conf)) + } > m_fcb_data + + .xmcd : + { + KEEP(*(.boot_hdr.xmcd_data)) + } > m_xmcd_data + + .container : + { + KEEP(*(.boot_hdr.container)) + } > m_container_data + + /* The startup code goes first */ + .interrupts : + { + . = ALIGN(4); + __Vectors = .; + KEEP(*(.isr_vector)) /* Vector table and startup code */ + . = ALIGN(4); + } > m_interrupts + + .interrupts_ram : + { + . = ALIGN(4); + . += __RAM_VECTOR_TABLE_SIZE_BYTES; + . = ALIGN(4); + } > m_interrupts_ram + + /* The program code */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(16); + core1_image_start = .; + KEEP (*(.core1_code)) + *(.core1_code*) + core1_image_end = .; + . = ALIGN(4) ; + } > m_text + + ASSERT((core1_image_end - core1_image_start) <= m_core1_image_maximum_size, "Core1 image size exceeds the limit") + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + + __data_flash_start = .; /* Symbol is used by startup for data initialization */ + .data : AT(__data_flash_start) + { + . = ALIGN(4); + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM code initialization */ + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + *(CodeQuickAccess) + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__noncache_data_flash_start) + { + . = ALIGN(4); + __noncache_data_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncache_data_end__ = .; /* create a global symbol at ncache data end */ + } > m_ncache + + .ncache : + { + . = ALIGN(4); + __noncache_bss_start__ = .; /* define a global symbol at ncache bss start */ + *(NonCacheable) + . = ALIGN(4); + __noncache_bss_end__ = .; /* define a global symbol at ncache bss end */ + } > m_ncache + + __qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__); + .qadata : AT(__qadata_flash_start) + { + . = ALIGN(4); + __qadata_start__ = .; + . = ALIGN(4); + __qadata_end__ = .; + } > m_qadata + + text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(text_data_end < text_end, "region m_text overflowed with text and data") + + __CONTAINER_IMG_SIZE = text_data_end - m_interrupts_start; + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > m_data + + .rpmsg : + { + *(.noinit.$rpmsg_sh_mem) + } > m_rpmsg + + .heap : + { + . = ALIGN(8); + __HeapBase = .; + end = .; + . += m_heap_size; + __HeapLimit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + __StackStart = .; + . += m_stack_size; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - m_stack_size; + PROVIDE(__stack = __StackTop); + PROVIDE (__stack_size = m_stack_size); + ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf new file mode 100644 index 00000000000..9ee6de8571d --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/board/linker_scripts/link.scf @@ -0,0 +1,232 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m33 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm33 +** MIMXRT1189CVM8C_cm33 +** MIMXRT1189XVM8B_cm33 +** MIMXRT1189XVM8C_cm33 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Board memory map */ + +#define m_code_tcm_start 0x0FFE0000 +#define m_code_tcm_size 0x00020000 + +#define m_system_tcm_start 0x20000000 +#define m_system_tcm_size 0x00020000 + +#define m_ocram1_start 0x20484000 /* OCRAM1 first 16K access is blocked by TRDC */ +#define m_ocram1_size 0x0007C000 + +#define m_ocram2_start 0x20500000 +#define m_ocram2_size 0x00040000 + +#if defined(__dual_image__) +/* CM33 use last 2M bytes space of sdram and hyperram for dual image framework */ +#define m_sdram_start 0x81E00000 +#define m_sdram_size 0x00200000 +#define m_hyperram_start 0x04600000 +#define m_hyperram_size 0x00200000 +#else +#define m_sdram_start 0x80000000 +#define m_sdram_size 0x02000000 +#define m_hyperram_start 0x04000000 +#define m_hyperram_size 0x00800000 +#endif + +#define m_flash_start 0x28000000 +#define m_flash_size 0x00800000 +#define m_core1_image_maximum_size 0x00040000 + +/* General definition */ +#define app_image_offset 0x0000B000 + +#define m_fcb_offset 0x400 +#define m_fcb_size 0x200 +#define m_xmcd_offset 0x800 +#define m_xmcd_size 0x400 +#define m_container_offset 0x1000 +#define m_container_size 0x2000 + +#define vector_table_size 0x400 +#define m_ram_vector_table_start m_code_tcm_start + +#if defined(__stack_size__) + #define stack_size __stack_size__ +#else + #define stack_size 0x01000 +#endif + +#if defined(__heap_size__) + #define heap_size __heap_size__ +#else + #define heap_size 0x04000 +#endif + +/* Target specific definition, code & data allocation */ +#if defined(__ram_vector_table__) +#define m_ram_vector_table_size vector_table_size +#else +#define m_ram_vector_table_size 0 +#endif + +#define m_qacode_start m_code_tcm_start + m_ram_vector_table_size +#define m_qadata_start m_system_tcm_start +#define m_qacode_size m_code_tcm_size - (m_qacode_start - m_code_tcm_start) +#define m_qadata_size 0 + +#define m_text_size m_flash_size - app_image_offset +#define m_data_size m_system_tcm_size +#if defined(__multicore__) +#define m_ncache_size 0x20000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0x40000 +#else +#define m_ncache_size 0x40000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0 +#endif +#define m_shmem_size m_ocram2_size /* m_shmem_size must be 2^N */ + +#define m_fcb_start m_flash_start + m_fcb_offset +#define m_xmcd_start m_flash_start + m_xmcd_offset +#define m_container_start m_flash_start + m_container_offset +#define m_text_start m_flash_start + app_image_offset +#define m_interrupts_start m_text_start +#define m_data_start m_system_tcm_start +#define m_ncache_start m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 - m_ncache_size +#define m_heap_start m_ocram1_start + +#if defined(__use_shmem__) +#define m_shmem_start m_ocram2_start +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +; load region +LR_m_header m_fcb_start (m_container_start) + (m_container_size) - (m_fcb_start) +{ + ; Flash Configuration Block + FCB m_fcb_start FIXED m_fcb_size + { + .ANY (.boot_hdr.conf) + } + + ; XMCD Block + XMCD m_xmcd_start FIXED m_xmcd_size + { + .ANY (.boot_hdr.xmcd_data) + } + + ; Container + Container m_container_start FIXED m_container_size + { + .ANY (.boot_hdr.container) + } + + ; Empty region added for container configuration + ER_m_container_image_offset (m_text_start) - (m_container_start) EMPTY 0 + { + } +} +#endif + +; load region +LR_m_text m_text_start m_text_size +{ + ; load address = execution address + VECTOR_ROM m_interrupts_start FIXED vector_table_size + { + * (.isr_vector,+FIRST) + } + + VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size + { + } + + ; load address = execution address + ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size + { + * (InRoot$$Sections) + .ANY (+RO) + } + + CORE1_REGION +0 ALIGN 16 m_core1_image_maximum_size + { + .ANY (.core1_code) + } + + ER_m_QuickAccessCode m_qacode_start m_qacode_size + { + .ANY (CodeQuickAccess) + } + + ER_m_QuickAccessData m_qadata_start EMPTY m_qadata_size + { + } + + RW_m_data m_data_start m_data_size-stack_size + { + .ANY (+RW +ZI) + .ANY (DataQuickAccess) + } + + ; ncache data + RW_m_ncache m_ncache_start m_ncache_size + { + .ANY (NonCacheable.init) + .ANY (.bss.NonCacheable) + } + +#if defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size + { + } +#endif + + ; Empty region added for MPU configuration + RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0 + { + } + +#if defined(__use_shmem__) + ; shared memory data + RPMSG_SH_MEM m_shmem_start m_shmem_size + { + .ANY (rpmsg_sh_mem_section) + } + + ; Empty region added for MPU configuration + RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0 + { + } +#endif + +#if !defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP m_heap_start EMPTY heap_size + { + } +#endif + + ; Stack region growing down + ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size + { + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_cm33.jlinkscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_cm33.jlinkscript new file mode 100644 index 00000000000..23137a7f748 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/evkmimxrt1180_cm33.jlinkscript @@ -0,0 +1,1041 @@ +__constant U32 _INDEX_AHB_AP_CORTEX_M33 = 3; +__constant U32 _AHB_ACC_32BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (2 << 0); +__constant U32 _AHB_ACC_16BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (1 << 0); // HMASTER = DEBUG, Private access, no Auto-increment, Access size: half word; +__constant U32 _ACCESS_AP = 1; +__constant U32 _CM33_CPUID = 0xD210; +__constant U32 _CM7_CPUID = 0x0C27; + +/* ROM trap address for CM33 core, after system reset */ +__constant U32 _ROM_TRAP0_ADDR = 0x10002932; +__constant U32 _ROM_TRAP1_ADDR = 0x100025D4; +__constant U32 _ROM_TRAP2_ADDR = 0x100025D4; + +__constant U32 _SRC_SRSR_ADDR = 0x44460050; +__constant U32 _SRC_SRMASK_ADDR = 0x44460018; +__constant U32 _SRC_SCR_ADDR = 0x44460010; +__constant U32 _SRC_AUTHEN_CTRL_ADDR = 0x44460004; +__constant U32 _SRC_SBMR2_ADDR = 0x44460044; +__constant U32 _BLK_M7_CFG_ADDR = 0x444F0080; + +__constant U32 _DWT_COMP0_ADDR = 0xE0001020; +__constant U32 _DWT_FUNC0_ADDR = 0xE0001028; + +__constant U32 _DCB_DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DCB_DEMCR_ADDR = 0xE000EDFC; + +__constant U32 _SCB_AIRCR_ADDR = 0xE000ED0C; + +__constant U32 _XCACHE_PC_CCR_ADDR = 0x44400000; +__constant U32 _XCACHE_PS_CCR_ADDR = 0x44400800; + +__constant U32 _CM33_MPU_CTRL_ADDR = 0xE000ED94; + +__constant U32 _SI_VER_ADDR = 0x5751804C; + +unsigned int cpuID; +unsigned int rom_trap_addr; + +static int _WriteViaCM33AP16(U32 Addr, U16 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + Data = (Data & 0xFFFF) | ((Data & 0xFFFF) << 16); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP16(U32 Addr) { + U32 r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +static int _WriteViaCM33AP32(U32 Addr, U32 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP32(U32 Addr) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +/* For Debug Start */ +__constant U32 _DCB_DCRSR_ADDR = 0xE000EDF4; +__constant U32 _DCB_DCRDR_ADDR = 0xE000EDF8; +__constant U32 _SCB_DFSR_ADDR = 0xE000ED30; + +__constant U32 _REG_R0 = 0x0; +__constant U32 _REG_R1 = 0x1; +__constant U32 _REG_R2 = 0x2; +__constant U32 _REG_R3 = 0x3; +__constant U32 _REG_R4 = 0x4; +__constant U32 _REG_R5 = 0x5; +__constant U32 _REG_R6 = 0x6; +__constant U32 _REG_R7 = 0x7; +__constant U32 _REG_R8 = 0x8; +__constant U32 _REG_R9 = 0x9; +__constant U32 _REG_R10 = 0xA; +__constant U32 _REG_R11 = 0xB; +__constant U32 _REG_R12 = 0xC; +__constant U32 _REG_SP = 0xD; +__constant U32 _REG_LR = 0xE; +__constant U32 _REG_PC = 0xF; +__constant U32 _REG_SP_main = 0x11; +__constant U32 _REG_SP_process = 0x12; +__constant U32 _REG_MSPLIM_S = 0x1C; +__constant U32 _REG_PSPLIM_S = 0x1D; +__constant U32 _REG_MSPLIM_NS = 0x1E; +__constant U32 _REG_PSPLIM_NS = 0x1F; + +static U32 _ReadCPUReg(int RegIndex) { + U32 v; + + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRSR_ADDR); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, RegIndex); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRDR_ADDR); + v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA); + return v; +} + +static U32 _ReadCPURegViaAP(int AP, int RegIndex) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (AP << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + + r = _ReadCPUReg(RegIndex); + return r; +} + +int debug = 0; + +void ShowDAPInfo(void) +{ + int r; + + if ( debug ) + { + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + r = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_CTRL); + JLINK_SYS_Report1("CM33 AP CSW = ", r); + } +} + +void DBG_ShowCM33Reg(void) +{ + int r, sp, pc; + + r = _ReadViaCM33AP32(_CM33_MPU_CTRL_ADDR); + JLINK_SYS_Report1(" CM33 MPU_CTRL = ", r); + r = _ReadViaCM33AP32(_XCACHE_PC_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PC_CCR = ", r); + r = _ReadViaCM33AP32(_XCACHE_PS_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PS_CCR = ", r); + + r = _ReadViaCM33AP32(_DWT_COMP0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_COMP0 = ", r); + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_FUNC0 = ", r); + + r = _ReadViaCM33AP32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" CM33 DFSR = ", r); + r = _ReadViaCM33AP32(_DCB_DEMCR_ADDR); + JLINK_SYS_Report1(" CM33 DEMCR = ", r); + r = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" CM33 DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_SP); + pc = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_PC); + JLINK_SYS_Report1(" CM33 PC = ", pc); + JLINK_SYS_Report1(" CM33 SP = ", sp); + } + else + { + JLINK_SYS_Report(" CM33 core is not halted!"); + } +} + +void DBG_ShowCoreReg(void) +{ + int r, sp, pc; + + r = JLINK_MEM_ReadU32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" DFSR = ", r); + r = JLINK_MEM_ReadU32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPUReg(_REG_SP); + pc = _ReadCPUReg(_REG_PC); + JLINK_SYS_Report1(" PC = ", pc); + JLINK_SYS_Report1(" SP = ", sp); + } + else + { + JLINK_SYS_Report(" Core is not halted!"); + } +} + +void DBG_ShowReg(int seq) +{ + int r; + if( debug ) + { + JLINK_SYS_Report1("Seq: ", seq); + + r = _ReadViaCM33AP32(_SRC_AUTHEN_CTRL_ADDR); + JLINK_SYS_Report1(" AUTHEN_CTRL = ", r); + r = _ReadViaCM33AP32(_SRC_SRSR_ADDR); + JLINK_SYS_Report1(" SRSR = ", r); + r = _ReadViaCM33AP32(_SRC_SRMASK_ADDR); + JLINK_SYS_Report1(" SRMASK = ", r); + r = _ReadViaCM33AP32(_SRC_SCR_ADDR); + JLINK_SYS_Report1(" SCR = ", r); + r = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + JLINK_SYS_Report1(" M7_CFG = ", r); + + if(cpuID == _CM7_CPUID) + { + if((r & 0x10) == 0) + { + DBG_ShowCoreReg(); + } + + } + + DBG_ShowCM33Reg(); + } +} +/* For Debug End */ + +void _FLEXSPI1_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI1_WaitBusIdle() +{ + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FLEXSPI1_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + MEM_WriteU32(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode for JLink + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + MEM_WriteU32(0x42A1023C, 0x17); + MEM_WriteU32(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + MEM_WriteU32(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + MEM_WriteU32(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + MEM_WriteU32(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + MEM_WriteU32(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + MEM_WriteU32(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + MEM_WriteU32(0x42A10254, 0x17); +} + +void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + MEM_WriteU32(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + MEM_WriteU32(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + MEM_WriteU32(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + MEM_WriteU32(0x425E0060, 0x00004000); + + + //FLEXSPI1->FLSHCR4 = 0xC3; + MEM_WriteU32(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + MEM_WriteU32(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + MEM_WriteU32(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + MEM_WriteU32(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + MEM_WriteU32(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + MEM_WriteU32(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + MEM_WriteU32(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + MEM_WriteU32(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + MEM_WriteU32(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + MEM_WriteU32(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + MEM_WriteU32(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + MEM_WriteU32(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + MEM_WriteU32(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + MEM_WriteU32(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + MEM_WriteU32(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + MEM_WriteU32(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + MEM_WriteU32(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + MEM_WriteU32(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + MEM_WriteU32(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + MEM_WriteU32(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + MEM_WriteU32(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + MEM_WriteU32(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + MEM_WriteU32(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + MEM_WriteU32(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + MEM_WriteU32(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + MEM_WriteU32(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + MEM_WriteU32(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + MEM_WriteU32(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + MEM_WriteU32(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + MEM_WriteU32(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + MEM_WriteU32(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + MEM_WriteU32(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + MEM_WriteU32(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + MEM_WriteU32(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + MEM_WriteU32(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + MEM_WriteU32(0x425E001C, 0x01); +} + +void _FLEXSPI2_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI2_WaitBusIdle() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FlexSPI2_SetPinForOctalMode() +{ + // Config IOMUX for FlexSPI2 + MEM_WriteU32(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + MEM_WriteU32(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + MEM_WriteU32(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +void _FLEXSPI2_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + MEM_WriteU32(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +void _FLEXSPI2_ModuleInit() +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0004, 0xFFFFFFFF); // MCR1 + MEM_WriteU32(0x445E0008, 0x200001F7); // MCR2 + MEM_WriteU32(0x445E000C, 0x00000078); // AHBCR prefetch enable + MEM_WriteU32(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + MEM_WriteU32(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + MEM_WriteU32(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + MEM_WriteU32(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + MEM_WriteU32(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + MEM_WriteU32(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + MEM_WriteU32(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + MEM_WriteU32(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + MEM_WriteU32(0x445E00B8, 0x00000000); // IPRXFCR + MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR + + MEM_WriteU32(0x445E0060, 0x00000000); // FLASHA1CR0 + MEM_WriteU32(0x445E0064, 0x00000000); // FLASHA2CR0 + MEM_WriteU32(0x445E0068, 0x00000000); // FLASHB1CR0 + MEM_WriteU32(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0060, 0x00002000); // FLASHA1CR0 + MEM_WriteU32(0x445E0070, 0x00021C63); // FLASHA1CR1 + MEM_WriteU32(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E00C0, 0x00000079); // DLLCRA + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = MEM_ReadU32(0x445E00E8); + } while (0x3 != (reg & 0x3)); + JLINK_SYS_Sleep(1); + // __delay(100);//100us + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0094, 0x000000C2); // FLASHCR4 + MEM_WriteU32(0x445E0094, 0x000000C6); // FLASHCR4 + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000002); // LUTCR + MEM_WriteU32(0x445E0200, 0x8B1887A0); // LUT[0] + MEM_WriteU32(0x445E0204, 0xB7078F10); // LUT[1] + MEM_WriteU32(0x445E0208, 0x0000A704); // LUT[2] + MEM_WriteU32(0x445E020C, 0x00000000); // LUT[3] + MEM_WriteU32(0x445E0210, 0x8B188720); // LUT[4] + MEM_WriteU32(0x445E0214, 0xB7078F10); // LUT[5] + MEM_WriteU32(0x445E0218, 0x0000A304); // LUT[6] + MEM_WriteU32(0x445E021C, 0x00000000); // LUT[7] + MEM_WriteU32(0x445E0220, 0x8B1887E0); // LUT[8] + MEM_WriteU32(0x445E0224, 0xB7078F10); // LUT[9] + MEM_WriteU32(0x445E0228, 0x0000A704); // LUT[10] + MEM_WriteU32(0x445E022C, 0x00000000); // LUT[11] + MEM_WriteU32(0x445E0230, 0x8B188760); // LUT[12] + MEM_WriteU32(0x445E0234, 0xA3028F10); // LUT[13] + MEM_WriteU32(0x445E0238, 0x00000000); // LUT[14] + MEM_WriteU32(0x445E023C, 0x00000000); // LUT[15] + MEM_WriteU32(0x445E0240, 0x00000000); // LUT[16] + MEM_WriteU32(0x445E0244, 0x00000000); // LUT[17] + MEM_WriteU32(0x445E0248, 0x00000000); // LUT[18] + MEM_WriteU32(0x445E024C, 0x00000000); // LUT[19] + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + MEM_WriteU32(0x445E00A0, 0x00001000); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + MEM_WriteU32(0x445E00A0, 0x00001002); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +void CM7_InitTCM(U32 targetAddr, U32 size) { + U32 reg; + + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + + if((reg & 0x80000000) != 0) + { + // DMA channel is active, wait it get finished + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + } + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag + + _WriteViaCM33AP32(0x5201002C, 0x00000000); // DMA4->TCD[0].SLAST_SGA + _WriteViaCM33AP32(0x52010038, 0x00000000); // DMA4->TCD[0].DLAST_SGA + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR + + _WriteViaCM33AP32(0x52010020, 0x20484000); // DMA4->TCD[0].SADDR + _WriteViaCM33AP32(0x52010030, targetAddr); // DMA4->TCD[0].DADDR + _WriteViaCM33AP32(0x52010028, size); // DMA4->TCD[0].NBYTES_MLOFFNO + _WriteViaCM33AP16(0x52010036, 0x1); // DMA4->TCD[0].ELINKNO + _WriteViaCM33AP16(0x5201003E, 0x1); // DMA4->TCD[0].BITER_ELINKNO + _WriteViaCM33AP16(0x52010026, 0x0303); // DMA4->TCD[0].ATTR + _WriteViaCM33AP16(0x52010024, 0x0); // DMA4->TCD[0].SOFF + _WriteViaCM33AP16(0x52010034, 0x8); // DMA4->TCD[0].DOFF + _WriteViaCM33AP32(0x52010000, 0x7); // DMA4->TDC[0].CH_CSR + _WriteViaCM33AP16(0x5201003C, 0x8); // DMA4->TCD[0].CSR + _WriteViaCM33AP16(0x5201003C, 0x9); // DMA4->TCD[0].CSR + + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag +} + +void CM7_KickOff(int ecc_init) +{ + U32 reg, resp1, resp2; + + reg = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + if((reg & 0x10) == 0) + { + JLINK_SYS_Report("CM7 is running already"); + } + else + { + JLINK_SYS_Report("************* Begin Operations to Enable CM7 ***********************"); + + // Clock Preparation + JLINK_SYS_Report("******** Prepare Clock *********"); + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + _WriteViaCM33AP32(0x54450000, 0x100); // CLOCK_ROOT[0].CONTROL, CM7 + + // Release CM7 + _WriteViaCM33AP32(_SRC_SCR_ADDR, 0x1); + + if (ecc_init) + { + // DMA initialization + JLINK_SYS_Report("******** DMA operation *********"); + CM7_InitTCM(0x303C0000, 0x40000); + CM7_InitTCM(0x30400000, 0x40000); + } + + // Making Landing Zone + JLINK_SYS_Report("******** Creating Landing Zone *********"); + _WriteViaCM33AP32(0x303C0000, 0x20020000); + _WriteViaCM33AP32(0x303C0004, 0x00000009); + _WriteViaCM33AP32(0x303C0008, 0xE7FEE7FE); + + // VTOR 0x00 + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0010); + + // Trigger ELE + JLINK_SYS_Report("******** ELE Trigger *********"); + _WriteViaCM33AP32(0x57540200, 0x17d20106); // MU_RT_S3MUA->TR[0] + resp1 = _ReadViaCM33AP32(0x57540280); // MU_RT_S3MUA->RR[0] + resp2 = _ReadViaCM33AP32(0x57540284); // MU_RT_S3MUA->RR[1] + JLINK_SYS_Report1("ELE RESP1 : ", resp1); + JLINK_SYS_Report1("ELE RESP2 : ", resp2); + + // Deassert CM7 Wait + JLINK_SYS_Report("******** Kickoff CM7 *********"); + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0); + } +} + +void DAP_Init(void) +{ + JLINK_CORESIGHT_Configure(""); + + CORESIGHT_AddAP(0, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(1, CORESIGHT_APB_AP); + CORESIGHT_AddAP(2, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(3, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(4, CORESIGHT_APB_AP); + CORESIGHT_AddAP(5, CORESIGHT_APB_AP); + CORESIGHT_AddAP(6, CORESIGHT_APB_AP); + + JLINK_SYS_Report("***************************************************"); + if(cpuID == _CM7_CPUID) + { + CPU = CORTEX_M7; + CORESIGHT_IndexAHBAPToUse = 2; + JLINK_SYS_Report("Current core is CM7"); + } + else if(cpuID == _CM33_CPUID) + { + CPU = CORTEX_M33; + CORESIGHT_IndexAHBAPToUse = 3; + JLINK_SYS_Report("Current core is CM33"); + + ShowDAPInfo(); + CORESIGHT_AHBAPCSWDefaultSettings = (1<<29)|(1<<25)|(1<<24); + } + else + { + JLINK_SYS_Report1("Wrong CPU ID: ", cpuID); + } + JLINK_SYS_Report("***************************************************"); +} + +void CM33_Halt(void) +{ + U32 reg; + + reg = (_ReadViaCM33AP32(_SRC_SBMR2_ADDR) >> 24) & 0x3F; + + if((reg == 8) || (reg == 9)) // Serial Download Mode, or Boot From Fuse + { + JLINK_SYS_Report("Not flash execution mode, check if CM33 is halted..."); + + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + + if(0 == (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is not halted, trying to halt it. CM33 DHCSR: ", reg); + + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0001); // Enable CM33 debug control + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Halt CM33 + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + if(0 != (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is halted now. CM33 DHCSR: ", reg); + } + else + { + JLINK_SYS_Report1("CM33 still running, halt failed. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report1("CM33 is halted. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report("Flash execution mode, leave CM33 run status as it was..."); + } +} + +void Flash_Init() { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init Flash"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void HyperRAM_Init() +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init HyperRAM"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void CM33_ClearNVIC(void) { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Clear NVIC"); + JLINK_SYS_Report("***************************************************"); + JLINK_MEM_Fill(0xE000E180, 0x40, 0xFF); + JLINK_MEM_Fill(0xE000E280, 0x40, 0xFF); +} + +int InitTarget(void) +{ + int r; + cpuID = _CM33_CPUID; + + DAP_Init(); + + if(cpuID == _CM7_CPUID) + { + CM33_Halt(); + CM7_KickOff(1); + + /* Avoid to access TPIU to prevent soc hang */ + JLINK_ExecCommand("map region 0xE0040000-0xE0040FFF X"); // Mark region as illegal + } + + r = _ReadViaCM33AP32(_SI_VER_ADDR) & 0xF; + + if ( r == 1 ) + { + rom_trap_addr = _ROM_TRAP1_ADDR; + } + else if ( r == 2 ) + { + rom_trap_addr = _ROM_TRAP2_ADDR; + } + else + { + rom_trap_addr = _ROM_TRAP0_ADDR; + } + JLINK_SYS_Report1("SI_VER = ", r); + JLINK_SYS_Report1("TRAP = ", rom_trap_addr); + + return 0; +} + +int SetupTarget(void) +{ + return 0; +} + +void ResetTarget_CM33(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + + core_reset_request_bit_mask = 0x100; /* for CM33 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM33 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM33 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + ShowDAPInfo(); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + JLINK_SYS_Report("Set CM33 watch point"); + comp = JLINK_MEM_ReadU32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later */ + func = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, rom_trap_addr); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, 0x00000412); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped!"); + } + + DBG_ShowReg(4); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM33 watch point"); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, comp); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM33 is not halted after reset!"); + } +} + +void ResetTarget_CM7(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + int mem_0, mem_1, mem_2; + + core_reset_request_bit_mask = 0x400; /* for CM7 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM7 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM7 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + /* CM7_KickOff will use the first 3 words(32bits) of CM7 ITCM, save and restore them later */ + mem_0 = JLINK_MEM_ReadU32(0); + mem_1 = JLINK_MEM_ReadU32(4); + mem_2 = JLINK_MEM_ReadU32(8); + + JLINK_SYS_Report("Set CM33 watch point"); + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Enable Debug and halt CM33 core + comp = _ReadViaCM33AP32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later after reset */ + func = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + _WriteViaCM33AP32(_DCB_DEMCR_ADDR, 0x01000000); // Enable DWT of CM33 core + _WriteViaCM33AP32(_DWT_COMP0_ADDR, rom_trap_addr); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, 0x00000412); + + DBG_ShowReg(4); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped after reset!"); + } + + DBG_ShowReg(5); + + CM7_KickOff(0); + + // Halt CM7 core + JLINK_MEM_WriteU32(_DCB_DHCSR_ADDR, 0xA05F0003); + + DBG_ShowReg(6); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM7 ITCM"); + + JLINK_MEM_WriteU32(0, mem_0); + JLINK_MEM_WriteU32(4, mem_1); + JLINK_MEM_WriteU32(8, mem_2); + + JLINK_SYS_Report("restore CM33 watch points"); + _WriteViaCM33AP32(_DWT_COMP0_ADDR, comp); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM7 core can not be halted!"); + } +} + +void ResetTarget(void) { + if(cpuID == _CM7_CPUID) + { + ResetTarget_CM7(); + } + else if(cpuID == _CM33_CPUID) + { + ResetTarget_CM33(); + } +} + +int AfterResetTarget(void) +{ + U32 reg; + + if(cpuID == _CM33_CPUID) + { + // CM33 NVIC may be enabled by ROM after reset + CM33_ClearNVIC(); + } + + Flash_Init(); + HyperRAM_Init(); + + return 0; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/figures/board.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/figures/board.png new file mode 100644 index 00000000000..19bde56131a Binary files /dev/null and b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/figures/board.png differ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h new file mode 100644 index 00000000000..3de0cab792c --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.h @@ -0,0 +1,437 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 4096 + +/* kservice options */ + +#define RT_USING_TINY_FFS +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_SECURE +#define ARCH_ARM_CORTEX_M33 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 4096 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +#define PKG_USING_CMBACKTRACE +#define PKG_CMBACKTRACE_PLATFORM_M33 +#define PKG_CMBACKTRACE_DUMP_STACK +#define PKG_CMBACKTRACE_PRINT_ENGLISH +#define PKG_USING_CMBACKTRACE_V10401 +#define PKG_CMBACKTRACE_VER_NUM 0x10401 +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +#define PKG_USING_NXP_IMXRT_DRIVER +#define PKG_USING_NXP_IMXRT_DRIVER_LATEST_VERSION +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_IMXRT1180_SERIES + +/* Hardware Drivers Config */ + +#define BSP_USING_QSPIFLASH +#define SOC_MIMXRT1189CVM8C +#define SOC_MIMXRT1189CVM8C_CM33 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_DMA +#define BSP_USING_LPUART +#define BSP_USING_LPUART1 +/* end of On-chip Peripheral Drivers */ + +/* Onboard Peripheral Drivers */ + +/* end of Onboard Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py new file mode 100644 index 00000000000..58d7d73accd --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/rtconfig.py @@ -0,0 +1,197 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 9.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +# BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__START=entry -D__STARTUP_CLEAR_BSS' + LFLAGS = DEVICE + ' -specs=nano.specs -specs=nosys.specs -Wl,--gc-sections,-Map=rtthread.map,--print-memory-usage -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + # AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA' + # AFLAGS += ' -D__STARTUP_CLEAR_BSS' + + if BUILD == 'debug': + CFLAGS += ' -g' + AFLAGS += ' -g' + # CFLAGS += ' -O1' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CXXFLAGS += CFLAGS + + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.scf"' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + CFLAGS += ' --diag_suppress=66,1296,186,6314' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + CFLAGS = ' --target=arm-arm-none-eabi' + CFLAGS += ' -mcpu=' + CPU + CFLAGS += ' -mfpu=fpv5-sp-d16' + CFLAGS += ' -mfloat-abi=hard' + CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + AFLAGS += ' -x assembler-with-cpp' + AFLAGS += ' -Wa,-mimplicit-it=thumb' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board/linker_scripts/link" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv5_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu VFPv5_sp' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + # sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp new file mode 100644 index 00000000000..6de7ddc90f8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.ewp @@ -0,0 +1,2172 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx new file mode 100644 index 00000000000..0dab8ecf45e --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvoptx @@ -0,0 +1,1188 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 33000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U603001820 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD30500000 -FC8000 -FN1 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33.FMIMXRT1180 CM33 FLEXSPI -FS028000000 -FL01000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC20000 -FN2 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FS028000000 -FL01000000 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FS128000000 -FL11000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\mnt.c + mnt.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Compiler + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\libc\compilers\common\cunistd.c + cunistd.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\core\device.c + device.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\ipc\completion_comm.c + completion_comm.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\ipc\completion_up.c + completion_up.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\ipc\condvar.c + condvar.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\pin\dev_pin.c + dev_pin.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\drivers\serial\dev_serial.c + dev_serial.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 23 + 1 + 0 + 0 + 0 + board\MCUX_Config\clock_config.c + clock_config.c + 0 + 0 + + + 4 + 24 + 1 + 0 + 0 + 0 + board\MCUX_Config\pin_mux.c + pin_mux.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + ..\libraries\drivers\drv_common.c + drv_common.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + ..\libraries\drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 5 + 28 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\..\..\src\cpu_up.c + cpu_up.c + 0 + 0 + + + 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+ ..\..\..\..\..\src\klibc\rt_vsscanf.c + rt_vsscanf.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + ..\..\..\..\..\src\klibc\kstdio.c + kstdio.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\..\..\..\..\src\klibc\kerrno.c + kerrno.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + ..\..\..\..\..\src\klibc\rt_vsnprintf_tiny.c + rt_vsnprintf_tiny.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + ..\..\..\..\..\src\klibc\kstring.c + kstring.c + 0 + 0 + + + + + libcpu + 0 + 0 + 0 + 0 + + 8 + 52 + 1 + 0 + 0 + 0 + ..\..\..\..\..\libcpu\arm\common\atomic_arm.c + atomic_arm.c + 0 + 0 + + + 8 + 53 + 1 + 0 + 0 + 0 + ..\..\..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 8 + 54 + 1 + 0 + 0 + 0 + ..\..\..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 8 + 55 + 2 + 0 + 0 + 0 + ..\..\..\..\..\libcpu\arm\cortex-m33\context_rvds.S + context_rvds.S + 0 + 0 + + + 8 + 56 + 1 + 0 + 0 + 0 + ..\..\..\..\..\libcpu\arm\cortex-m33\cpuport.c + cpuport.c + 0 + 0 + + + 8 + 57 + 2 + 0 + 0 + 0 + ..\..\..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S + syscall_rvds.S + 0 + 0 + + + 8 + 58 + 1 + 0 + 0 + 0 + ..\..\..\..\..\libcpu\arm\cortex-m33\trustzone.c + trustzone.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 9 + 59 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_memory.c + fsl_memory.c + 0 + 0 + + + 9 + 60 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_pmu.c + fsl_pmu.c + 0 + 0 + + + 9 + 61 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\utilities\debug_console_lite\fsl_assert.c + fsl_assert.c + 0 + 0 + + + 9 + 62 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\cm33\fsl_cache.c + fsl_cache.c + 0 + 0 + + + 9 + 63 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_gpc.c + fsl_gpc.c + 0 + 0 + + + 9 + 64 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_soc_src.c + fsl_soc_src.c + 0 + 0 + + + 9 + 65 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_trdc.c + fsl_trdc.c + 0 + 0 + + + 9 + 66 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_rgpio.c + fsl_rgpio.c + 0 + 0 + + + 9 + 67 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_ele_base_api.c + fsl_ele_base_api.c + 0 + 0 + + + 9 + 68 + 2 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\arm\startup_MIMXRT1189_cm33.s + startup_MIMXRT1189_cm33.s + 0 + 0 + + + 9 + 69 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\system_MIMXRT1189_cm33.c + system_MIMXRT1189_cm33.c + 0 + 0 + + + 9 + 70 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_clock.c + fsl_clock.c + 0 + 0 + + + 9 + 71 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_common.c + fsl_common.c + 0 + 0 + + + 9 + 72 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_lpuart.c + fsl_lpuart.c + 0 + 0 + + + 9 + 73 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_dcdc.c + fsl_dcdc.c + 0 + 0 + + + 9 + 74 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_common_arm.c + fsl_common_arm.c + 0 + 0 + + + 9 + 75 + 1 + 0 + 0 + 0 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_s3mu.c + fsl_s3mu.c + 0 + 0 + + + + + xip + 0 + 0 + 0 + 0 + + 10 + 76 + 1 + 0 + 0 + 0 + xip\fsl_flexspi_nor_boot.c + fsl_flexspi_nor_boot.c + 0 + 0 + + + 10 + 77 + 1 + 0 + 0 + 0 + xip\evkmimxrt1180_flexspi_nor_config.c + evkmimxrt1180_flexspi_nor_config.c + 0 + 0 + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx new file mode 100644 index 00000000000..cef821f2bc6 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/template.uvprojx @@ -0,0 +1,2216 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 6220000::V6.22::ARMCLANG + 1 + + + MIMXRT1189CVM8C:cm33 + NXP + NXP.MIMXRT1189_DFP.25.06.00 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + CPUTYPE("Cortex-M33") FPU3(SFPU) TZ DSP ELITTLE + + + + 0 + $$Device:MIMXRT1189CVM8B$fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1189CVM8B$MIMXRT1189_cm33.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMV8M.DLL + -REMAP -MPU + DCM.DLL + -pCM33 + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + "Cortex-M33" + + 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ARM_MATH_CM33, XIP_BOOT_HEADER_DCD_ENABLE=1 + + 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packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_soc_src.c + + + fsl_trdc.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_trdc.c + + + fsl_rgpio.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_rgpio.c + + + fsl_ele_base_api.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_ele_base_api.c + + + startup_MIMXRT1189_cm33.s + 2 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\arm\startup_MIMXRT1189_cm33.s + + + system_MIMXRT1189_cm33.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\system_MIMXRT1189_cm33.c + + + fsl_clock.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_clock.c + + + fsl_common.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_common.c + + + fsl_lpuart.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_lpuart.c + + + fsl_dcdc.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_dcdc.c + + + fsl_common_arm.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_common_arm.c + + + fsl_s3mu.c + 1 + packages\nxp-imxrt-sdk-latest\MIMXRT1180\MIMXRT1189\drivers\fsl_s3mu.c + + + + + xip + + + fsl_flexspi_nor_boot.c + 1 + xip\fsl_flexspi_nor_boot.c + + + evkmimxrt1180_flexspi_nor_config.c + 1 + xip\evkmimxrt1180_flexspi_nor_config.c + + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/SConscript new file mode 100644 index 00000000000..88aa7fb12a7 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/SConscript @@ -0,0 +1,20 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +if GetDepend('BSP_USING_QSPIFLASH'): + cwd = GetCurrentDir() + src = Glob('*.c') + CPPPATH = [cwd] + LINKFLAGS = '' + + if rtconfig.PLATFORM in ['armcc', 'armclang']: + LINKFLAGS += ' --keep=*(.boot_hdr.container)' + # LINKFLAGS += ' --keep=*(.boot_hdr.xmcd_data)' + LINKFLAGS += ' --keep=*(.boot_hdr.conf)' + LINKFLAGS += ' --entry=Reset_Handler ' + LINKFLAGS += ' --predefine="-DXIP_BOOT_HEADER_ENABLE=1"' + LINKFLAGS += ' --predefine="-DXIP_EXTERNAL_FLASH=1"' + + group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS) + Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.c new file mode 100644 index 00000000000..b40c379460f --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.c @@ -0,0 +1,120 @@ +/* + * Copyright 2018-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkmimxrt1180_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/* clang-format off */ +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) && \ + defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +/* clang-format on */ + +#if defined(USE_HYPERRAM) + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.xmcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.xmcd_data" +#endif + +const uint32_t xmcd_data[] = { + 0xC002000C, /* FlexSPI instance 2 */ + 0xC1000800, /* Option words = 2 */ + 0x00010000 /* PINMUX Secondary group */ +}; + +#endif + +#if defined(USE_SDRAM) + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.xmcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.xmcd_data" +#endif + +const uint32_t xmcd_data[] = { + 0xC010000D, /* SEMC -> SDRAM */ + 0xA60001A1, /* SDRAM config */ + 0x00008000, /* SDRAM config */ + 0X00000001 /* SDRAM config */ +}; + +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +/* + * FlexSPI nor flash configuration block + * Note: + * Below setting is special for EVK board flash, to achieve maximum access performance. + * For other boards or flash, may leave it 0 or delete fdcb_data, which means auto probe. + */ + +/* clang-format off */ +#define FLASH_DUMMY_CYCLES 0x06 + +const flexspi_nor_config_t qspi_flash_nor_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = 0x10, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 16u * 1024u * 1024u, + + .configModeType[0] = kDeviceConfigCmdType_Generic, + + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, FLASH_DUMMY_CYCLES, READ_SDR, FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 0x1, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +/* clang-format on */ + +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.h new file mode 100644 index 00000000000..9b73d5947c1 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/evkmimxrt1180_flexspi_nor_config.h @@ -0,0 +1,190 @@ +/* + * Copyright 2018-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ + +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_DEVICE driver version 2.0.4. */ +#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_Reversed = 2, + kFlexSPIReadSampleClk_FlashProvidedDqs = 3, +} flexspi_read_sample_clk_t; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3 //!< Flash devices are Serial RAM/HyperFLASH +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, +} flexspi_serial_clk_freq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t isDataOrderSwapped; //!< The data order is swapped in OPI DDR mode + uint8_t reserved0[5]; //!< Reserved for future use + uint32_t blockSize; //!< Block size + uint32_t FlashStateCtx; //!< Flash State Context after being configured + uint32_t reserve1[10]; //!< Reserved for future use +} flexspi_nor_config_t; + + +#endif /* __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.c new file mode 100644 index 00000000000..773275023cf --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.c @@ -0,0 +1,64 @@ +/* + * Copyright 2021-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexspi_nor_boot.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_device" +#endif + +/* clang-format off */ +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) && \ + defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +/* clang-format on */ + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.container"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.container" +#endif + +/* clang-format off */ +const container container_data = +{ + { + CNT_VERSION, + CNT_SIZE, + CNT_TAG_HEADER, + CNT_FLAGS, + CNT_SW_VER, + CNT_FUSE_VER, + CNT_NUM_IMG, + sizeof(cnt_hdr) + CNT_NUM_IMG * sizeof(image_entry), + 0 + }, + {{ + IMAGE_OFFSET, + IMAGE_SIZE, + IMAGE_LOAD_ADDRESS, + 0x00000000, + IMAGE_ENTRY_ADDRESS, + 0x00000000, + IMG_FLAGS, + 0x0, + {0}, + {0} + }}, + { + SGNBK_VERSION, + SGNBK_SIZE, + SGNBK_TAG, + 0x0, + 0x0, + 0x0, + 0x0 + } +}; +/* clang-format on */ + +#endif \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.h new file mode 100644 index 00000000000..587b18b7f28 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm33/xip/fsl_flexspi_nor_boot.h @@ -0,0 +1,122 @@ +/* + * Copyright 2021-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FLEXSPI_NOR_BOOT_H__ +#define __FLEXSPI_NOR_BOOT_H__ + +#include "fsl_common.h" + +/************************************* + * Container + *************************************/ +/* Container header */ +#define CNT_TAG_HEADER 0x87 +#define CNT_SIZE (uint16_t)(sizeof(container)) +#define CNT_VERSION 0x00 +#define CNT_NUM_IMG 1 +#define CNT_FUSE_VER 0 +#define CNT_SW_VER 0 +#define CNT_FLAGS 0x00000000 // Container not authenticated + +#define IMG_FLAGS 0x00000213 // Non-encrypted, SHA512, CM33, Executable + +#define SGNBK_TAG 0x90 +#define SGNBK_SIZE (uint16_t)(sizeof(sign_block)) +#define SGNBK_VERSION 0x00 + +typedef struct __attribute__((packed)) _cnt_hdr_ +{ + uint8_t version; + uint16_t length; + uint8_t tag; + + uint32_t flags; + + uint16_t sw_ver; + uint8_t fuse_ver; + uint8_t num_images; + + uint16_t sign_blk_offset; + uint16_t reserved1; +} cnt_hdr; + +typedef struct __attribute__((packed)) _img_entry_ +{ + uint32_t offset; + uint32_t size; + uint32_t load_addr; + uint32_t reserved1; + uint32_t entry; + uint32_t reserved2; + uint32_t flags; + uint32_t metadata; + uint8_t hash[64]; + uint8_t iv[32]; +} image_entry; + +typedef struct __attribute__((packed)) _sign_block_ +{ + uint8_t version; + uint16_t length; + uint8_t tag; + + uint16_t cert_offset; + uint16_t srk_offset; + uint16_t sign_offset; + uint16_t blob_offset; + uint32_t reserved1; + uint8_t data[0]; +} sign_block; + +typedef struct __attribute__((packed)) _container_ +{ + cnt_hdr hdr; + image_entry array[CNT_NUM_IMG]; + sign_block sign_block; +} container; + +/* Set resume entry */ +#if defined(__MCUXPRESSO) +extern uint32_t app_image_offset[]; +extern uint32_t _image_size[]; +extern uint32_t _image_loadaddr[]; +extern uint32_t ResetISR[]; +#define IMAGE_OFFSET ((uint32_t)app_image_offset) +#define IMAGE_SIZE ((uint32_t)_image_size) +#define IMAGE_LOAD_ADDRESS ((uint32_t)_image_loadaddr) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)ResetISR) + +#elif defined(__ICCARM__) +#pragma section = "RO" +extern uint32_t __CONTAINER_IMG_OFFSET[]; +extern uint32_t __CONTAINER_IMG_LOAD_ADDR[]; +extern uint32_t __CONTAINER_IMG_ENTRY_ADDR[]; +#define IMAGE_OFFSET ((uint32_t)__CONTAINER_IMG_OFFSET) +#define IMAGE_SIZE ((uint32_t)__section_size("RO")) +#define IMAGE_LOAD_ADDRESS ((uint32_t)__CONTAINER_IMG_LOAD_ADDR) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__CONTAINER_IMG_ENTRY_ADDR) + +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +extern uint32_t Image$$ER_m_container_image_offset$$ZI$$Base[]; +extern uint32_t Image$$VECTOR_ROM$$Base[]; +extern uint32_t Load$$LR$$LR_m_text$$Length[]; +#define IMAGE_OFFSET ((uint32_t)Image$$ER_m_container_image_offset$$ZI$$Base) +#define IMAGE_SIZE ((uint32_t)Load$$LR$$LR_m_text$$Length) +#define IMAGE_LOAD_ADDRESS ((uint32_t)Image$$VECTOR_ROM$$Base) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)Image$$VECTOR_ROM$$Base) + +#elif defined(__GNUC__) +extern uint32_t __CONTAINER_IMG_OFFSET[]; +extern uint32_t __CONTAINER_IMG_SIZE[]; +extern uint32_t __VECTOR_TABLE[]; +#define IMAGE_OFFSET ((uint32_t)__CONTAINER_IMG_OFFSET) +#define IMAGE_SIZE ((uint32_t)__CONTAINER_IMG_SIZE) +#define IMAGE_LOAD_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#endif + +#endif /* __FLEXSPI_NOR_BOOT_H__ */ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config new file mode 100644 index 00000000000..1ae4165032d --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/.config @@ -0,0 +1,1488 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_ARCH_USING_HW_ATOMIC_8=y +CONFIG_ARCH_USING_HW_ATOMIC_16=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_M33=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_NES_SIMULATOR is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_VECTOR is not set +CONFIG_PKG_USING_CMBACKTRACE=y +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M0_M0PLUS is not set +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M3 is not set +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M4 is not set +# CONFIG_PKG_CMBACKTRACE_PLATFORM_M7 is not set +CONFIG_PKG_CMBACKTRACE_PLATFORM_M33=y +# CONFIG_PKG_CMBACKTRACE_PLATFORM_NOT_SELECTED is not set +CONFIG_PKG_CMBACKTRACE_DUMP_STACK=y +CONFIG_PKG_CMBACKTRACE_PRINT_ENGLISH=y +# CONFIG_PKG_CMBACKTRACE_PRINT_CHINESE is not set +# CONFIG_PKG_CMBACKTRACE_PRINT_CHINESE_UTF8 is not set +# CONFIG_CMB_USING_FAL_FLASH_LOG is not set +CONFIG_PKG_CMBACKTRACE_PATH="/packages/tools/CmBacktrace" +CONFIG_PKG_USING_CMBACKTRACE_V10401=y +# CONFIG_PKG_USING_CMBACKTRACE_V10400 is not set +# CONFIG_PKG_USING_CMBACKTRACE_V10300 is not set +# CONFIG_PKG_USING_CMBACKTRACE_V10202 is not set +# CONFIG_PKG_USING_CMBACKTRACE_V10200 is not set +# CONFIG_PKG_USING_CMBACKTRACE_LATEST_VERSION is not set +CONFIG_PKG_CMBACKTRACE_VER="v1.4.1" +CONFIG_PKG_CMBACKTRACE_VER_NUM=0x10401 +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# CONFIG_PKG_USING_UORB is not set +# CONFIG_PKG_USING_RT_TUNNEL is not set +# CONFIG_PKG_USING_VIRTUAL_TERMINAL is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# CONFIG_PKG_USING_CHERRYECAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +CONFIG_PKG_USING_NXP_IMXRT_DRIVER=y +CONFIG_PKG_NXP_IMXRT_DRIVER_PATH="/packages/peripherals/hal-sdk/nxp/nxp-imxrt-sdk" +CONFIG_PKG_USING_NXP_IMXRT_DRIVER_LATEST_VERSION=y +CONFIG_PKG_NXP_IMXRT_DRIVER_VER="latest" +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32_RISCV_SERIES_DRIVER is not set +# CONFIG_PKG_USING_GD32VW55X_WIFI is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +# CONFIG_PKG_USING_HPM_SDK is not set +# end of HPMicro SDK + +# +# FT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_FT32F0_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_STD_DRIVER is not set +# CONFIG_PKG_USING_FT32F4_CMSIS_DRIVER is not set +# end of FT32 HAL & SDK Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90384 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90396 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# CONFIG_PKG_USING_SCD4X is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_LCD_SPI_DRIVER is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_CAN_UDS is not set +# CONFIG_PKG_USING_ISOTP_C is not set +# CONFIG_PKG_USING_IKUNLED is not set +# CONFIG_PKG_USING_INS5T8025 is not set +# CONFIG_PKG_USING_ST7305 is not set +# CONFIG_PKG_USING_TM1668 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_IMXRT1180_SERIES=y + +# +# Hardware Drivers Config +# +CONFIG_BSP_USING_QSPIFLASH=y +CONFIG_SOC_MIMXRT1189CVM8C=y +CONFIG_SOC_MIMXRT1189CVM8C_CM7=y + +# +# On-chip Peripheral Drivers +# +# CONFIG_BSP_USING_DMA is not set +# CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_SDIO is not set +CONFIG_BSP_USING_LPUART=y +CONFIG_BSP_USING_LPUART1=y +# CONFIG_BSP_LPUART1_RX_USING_DMA is not set +# CONFIG_BSP_LPUART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_LPUART3 is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_FLEXSPI is not set +# end of On-chip Peripheral Drivers + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_SDRAM is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_FS is not set +# CONFIG_BSP_USING_VGLITE is not set +# end of Onboard Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/JLinkSettings.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/JLinkSettings.ini new file mode 100644 index 00000000000..c2434b347af --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/JLinkSettings.ini @@ -0,0 +1,45 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +MaxNumTransfers = 0x00 +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x00 +[DYN_MEM_MAP] +NumUserRegion = 0x00 diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/Kconfig new file mode 100644 index 00000000000..91fa11dd5da --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/Kconfig @@ -0,0 +1,10 @@ +mainmenu "RT-Thread Configuration" + +RTT_DIR := ../../../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConscript new file mode 100644 index 00000000000..c7ef7659ece --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConstruct b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConstruct new file mode 100644 index 00000000000..644e0534ecc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/SConstruct @@ -0,0 +1,88 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("..", "packages", "nxp-imxrt-sdk-latest"), + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +DefaultEnvironment(tools=[]) +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./..') +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +imxrt_library = 'MIMXRT1180' +rtconfig.BSP_LIBRARY_TYPE = imxrt_library + +# include libraries +objs.extend(SConscript(os.path.join("..", "packages/nxp-imxrt-sdk-latest", imxrt_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript new file mode 100644 index 00000000000..8f55fb0d82f --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/SConscript @@ -0,0 +1,17 @@ +import rtconfig +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +# add for startup script +if rtconfig.PLATFORM in ['gcc']: + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c new file mode 100644 index 00000000000..5c4b4373dfd --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/applications/main.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-05-06 tyustli first version + * + */ + +#include +#include +#include +#include + +int main(void) +{ + rt_kprintf("MIMXRT1180_CM7 Hello_World\r\n"); + + while (1) + { + rt_thread_mdelay(500); + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig new file mode 100644 index 00000000000..d2cdad35fc1 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/Kconfig @@ -0,0 +1,278 @@ +menu "Hardware Drivers Config" + +config BSP_USING_QSPIFLASH + bool + default n + +config SOC_MIMXRT1189CVM8C + bool + select SOC_IMXRT1180_SERIES + select BSP_USING_QSPIFLASH + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config SOC_MIMXRT1189CVM8C_CM7 + bool + default y + depends on SOC_MIMXRT1189CVM8C + +config BSP_USING_LCD_MIPI + bool + default n + +menu "On-chip Peripheral Drivers" + + config BSP_USING_DMA + bool "Enable DMA" + default n + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + config BSP_USING_USB + bool "Enable USB" + select RT_USING_USB_HOST + default n + + if BSP_USING_USB + config BSP_USB0_HOST + bool "Enable USB0" + default n + + config BSP_USB1_HOST + bool "Enable USB1" + default n + endif + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + if BSP_USING_SDIO + config CODE_STORED_ON_SDCARD + bool "Enable Code STORED On SDCARD" + default n + help + "SD CARD work as boot devive" + endif + + menuconfig BSP_USING_LPUART + bool "Enable UART" + select RT_USING_SERIAL + default y + + if BSP_USING_LPUART + config BSP_USING_LPUART1 + bool "Enable LPUART1" + default y + + config BSP_LPUART1_RX_USING_DMA + bool "Enable LPUART1 RX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_RX_DMA_CHANNEL + depends on BSP_LPUART1_RX_USING_DMA + int "Set LPUART1 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART1_TX_USING_DMA + bool "Enable LPUART1 TX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_TX_DMA_CHANNEL + depends on BSP_LPUART1_TX_USING_DMA + int "Set LPUART1 TX DMA channel (0-32)" + default 1 + + config BSP_USING_LPUART3 + bool "Enable LPUART3" + default n + + config BSP_LPUART3_RX_USING_DMA + bool "Enable LPUART3 RX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_RX_DMA_CHANNEL + depends on BSP_LPUART3_RX_USING_DMA + int "Set LPUART3 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART3_TX_USING_DMA + bool "Enable LPUART3 TX DMA" + depends on BSP_USING_LPUART3 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART3_TX_DMA_CHANNEL + depends on BSP_LPUART3_TX_USING_DMA + int "Set LPUART3 TX DMA channel (0-32)" + default 1 + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + select RT_USING_CAN + default n + if BSP_USING_CAN + config BSP_USING_CAN3 + bool "Enable FLEXCAN3" + default n + endif + + menuconfig BSP_USING_FLEXSPI + bool "Enable FLEXSPI" + default n + if BSP_USING_FLEXSPI + config BSP_USING_FLEXSPI1 + bool "Enable FLEXSPI1" + default n + config BSP_USING_FLEXSPI2 + bool "Enable FLEXSPI2" + default n + endif +endmenu + +menu "Onboard Peripheral Drivers" + + config BSP_USING_SDRAM + bool "Enable SDRAM" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_NETDEV + select RT_USING_LWIP + default n + + + if BSP_USING_ETH + config BSP_USING_PHY + select RT_USING_PHY + bool "Enable ethernet phy" + default y + + if BSP_USING_PHY + config PHY_USING_KSZ8081 + bool "i.MX RT1176EVK uses ksz8081 phy" + default y + + if PHY_USING_KSZ8081 + config PHY_KSZ8081_ADDRESS + int "Specify address of phy device" + default 2 + + config PHY_RESET_KSZ8081_PORT + int "indicate port of reset" + default 6 + + config PHY_RESET_KSZ8081_PIN + int "indicate pin of reset" + default 12 + + config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE + bool "Enable the PHY ksz8081 RMII50M mode" + depends on PHY_USING_KSZ8081 + default y + endif + endif + + if BSP_USING_PHY + config PHY_USING_RTL8211F + bool "i.MX RT1176EVK uses rtl8211f phy" + default y + + if PHY_USING_RTL8211F + config PHY_RTL8211F_ADDRESS + int "Specify address of phy device" + default 1 + + config PHY_RESET_RTL8211F_PORT + int "indicate port of reset" + default 5 + + config PHY_RESET_RTL8211F_PIN + int "indicate pin of reset" + default 14 + + endif + endif + endif + + menuconfig BSP_USING_FS + bool "Enable File System" + select RT_USING_DFS_DEVFS + select RT_USING_DFS + default n + + if BSP_USING_FS + config BSP_USING_SDCARD_FATFS + bool "Enable SDCARD (FATFS)" + select BSP_USING_SDIO + select RT_USING_DFS_ELMFAT + default n + endif + + menuconfig BSP_USING_VGLITE + bool "Enable VGLite" + select RT_USING_PIN + select BSP_USING_LCD_MIPI + default n + + if BSP_USING_VGLITE + choice + prompt "Select display panel" + default DISPLAY_USING_RK055AHD091 + + config DISPLAY_USING_RK055AHD091 + bool "RK055AHD091-CTG (RK055HDMIPI4M 720 * 1280)" + + config DISPLAY_USING_RK055IQH091 + bool "RK055IQH091-CTG (540 * 960)" + + config DISPLAY_USING_RK055MHD091 + bool "RK055MHD091A0-CTG (RK055HDMIPI4MA0 720 * 1280)" + endchoice + + choice + prompt "Select display controller" + default BSP_USING_LCDIFV2 + + config BSP_USING_ELCDIF + bool "ELCDIF" + + config BSP_USING_LCDIFV2 + bool "LCDIFV2" + endchoice + + config VGLITE_USING_ELM + bool "Enable Elementary" + default y + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/MCUX_Config.mex b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/MCUX_Config.mex new file mode 100644 index 00000000000..85d03f19933 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/MCUX_Config.mex @@ -0,0 +1,596 @@ + + + + MIMXRT1176xxxxx + MIMXRT1176DVMAA + ksdk2_0 + + + + + + + + true + false + false + true + false + + + + + 12.0.0 + + + + + Configures pin routing and optionally pin electrical features. + + true + cm7 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 12.0.0 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + 12.0.0 + c_array + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 12.0.0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + N/A + + + + \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.c new file mode 100644 index 00000000000..7c1d7f6afdf --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.c @@ -0,0 +1,836 @@ +/* + * Copyright 2022-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v13.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 0.0.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_misc.h" +#include "fsl_dcdc.h" +#include "fsl_pmu.h" +#include "fsl_clock.h" +#include "fsl_ele_base_api.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_FlexspiClockSafeConfig + * Description : FLEXSPI clock source safe configuration weak function. + * Called before clock source configuration. + * Note : Users need override this function to change FLEXSPI clock source to stable source when executing + * code on FLEXSPI memory(XIP). If XIP, the function should runs in RAM and move the FLEXSPI clock source + * to a stable clock to avoid instruction/data fetch issue during clock updating. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_FlexspiClockSafeConfig(void) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_SetFlexspiClock + * Description : This function should be overridden if executing code on FLEXSPI memory(XIP). + * To Change FLEXSPI clock, should move to run from RAM and then configure FLEXSPI clock source. + * After the clock is changed and stable, move back to run on FLEXSPI. + * Param base : FLEXSPI peripheral base address. + * Param src : FLEXSPI clock source. + * Param divider : FLEXSPI clock divider. + *END**************************************************************************/ +__attribute__((weak)) void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint8_t src, uint32_t divider) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : EdgeLock_SetClock + * Description : Set EdgeLock clock via safe method + * Note : It requires specific sequence to change edgelock clock source, + * otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void EdgeLock_SetClock(uint8_t mux, uint8_t div) +{ +} + +/*FUNCTION********************************************************************** + * + * Function Name : DCDC_SetVoltage + * Description : Set DCDC voltage via safe method + * Note : It requires specific sequence to change DCDC voltage when GDET + * is enabled, otherwise the soc behavior is unpredictable. + *END**************************************************************************/ +__attribute__((weak)) void DCDC_SetVoltage(uint8_t core, uint8_t targetVoltage) +{ +} + + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ACMP_CLK_ROOT.outFreq, value: 240 MHz} +- {id: ADC1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: ADC2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: ARM_PLL_CLK.outFreq, value: 792 MHz} +- {id: ASRC_CLK_ROOT.outFreq, value: 240 MHz} +- {id: BUS_AON_CLK_ROOT.outFreq, value: 132 MHz} +- {id: BUS_WAKEUP_CLK_ROOT.outFreq, value: 132 MHz} +- {id: CAN1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CAN3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CCM_CKO1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: CCM_CKO2_CLK_ROOT.outFreq, value: 50 MHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: ECAT_CLK_ROOT.outFreq, value: 100 MHz} +- {id: ECAT_PORT0_REF_CLK.outFreq, value: 50 MHz} +- {id: ECAT_PORT1_REF_CLK.outFreq, value: 50 MHz} +- {id: EDGELOCK_CLK_ROOT.outFreq, value: 200 MHz} +- {id: ENET_REFCLK_ROOT.outFreq, value: 125 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 120 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 48 MHz} +- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2160/11 MHz} +- {id: FLEXSPI_SLV_CLK_ROOT.outFreq, value: 132 MHz} +- {id: GPT1_CLK_ROOT.outFreq, value: 240 MHz} +- {id: GPT2_CLK_ROOT.outFreq, value: 240 MHz} +- {id: I3C1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: I3C2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C0102_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0304_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPI2C0506_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPIT3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPSPI0102_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPSPI0304_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPSPI0506_CLK_ROOT.outFreq, value: 1440/11 MHz} +- {id: LPTMR1_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPTMR3_CLK_ROOT.outFreq, value: 80 MHz} +- {id: LPUART0102_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0304_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0506_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0708_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART0910_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART1112_CLK_ROOT.outFreq, value: 24 MHz} +- {id: M33_CLK_ROOT.outFreq, value: 240 MHz} +- {id: M33_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: M7_CLK_ROOT.outFreq, value: 792 MHz} +- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: MAC0_CLK_ROOT.outFreq, value: 50 MHz} +- {id: MAC1_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC2_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC3_CLK_ROOT.outFreq, value: 125 MHz} +- {id: MAC4_CLK_ROOT.outFreq, value: 50 MHz} +- {id: MIC_CLK_ROOT.outFreq, value: 80 MHz} +- {id: NETC_CLK_ROOT.outFreq, value: 240 MHz} +- {id: NETC_PORT0_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT1_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT2_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT3_REF_CLK.outFreq, value: 50 MHz} +- {id: NETC_PORT4_REF_CLK.outFreq, value: 50 MHz} +- {id: OSC_24M.outFreq, value: 24 MHz} +- {id: OSC_32K.outFreq, value: 32.768 kHz} +- {id: OSC_RC_24M.outFreq, value: 24 MHz} +- {id: OSC_RC_400M.outFreq, value: 400 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 200 MHz} +- {id: SWO_TRACE_CLK_ROOT.outFreq, value: 80 MHz} +- {id: SYS_PLL1_CLK.outFreq, value: 1 GHz} +- {id: SYS_PLL1_DIV2_CLK.outFreq, value: 500 MHz} +- {id: SYS_PLL1_DIV5_CLK.outFreq, value: 200 MHz} +- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz} +- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz} +- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz} +- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz} +- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz} +- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz} +- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz} +- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 4320/11 MHz} +- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 2880/11 MHz} +- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 4320/11 MHz} +- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 480 MHz} +- {id: TMR_1588_CLK_ROOT.outFreq, value: 240 MHz} +- {id: TMR_1588_REF_CLK.outFreq, value: 240 MHz} +- {id: TPM2_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM4_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM5_CLK_ROOT.outFreq, value: 80 MHz} +- {id: TPM6_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 396 MHz} +- {id: WAKEUP_AXI_CLK_ROOT.outFreq, value: 240 MHz} +settings: +- {id: AONDomainVoltage, value: OD} +- {id: CoreClockRootsInitializationConfig, value: selectedCore} +- {id: SOCDomainVoltage, value: OD} +- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low} +- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled} +- {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '2', locked: true} +- {id: ANADIG_PLL.ARM_PLL_PREDIV.scale, value: '1', locked: true} +- {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '132', locked: true} +- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M} +- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455', locked: true} +- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'} +- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'} +- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'} +- {id: ANADIG_PLL.SYS_PLL3_PFD0_DIV.scale, value: '22'} +- {id: ANADIG_PLL.SYS_PLL3_PFD1_DIV.scale, value: '33', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD1_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD2_DIV.scale, value: '22', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD2_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '18'} +- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled} +- {id: CCM.CLOCK_ROOT0.DIV.scale, value: '1', locked: true} +- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK} +- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT10.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT10.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT11.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT11.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT12.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT12.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT13.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT13.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT14.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT14.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT15.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT15.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT16.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT16.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT17.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT17.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT18.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT18.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT19.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_OSC.OSC_RC_400M} +- {id: CCM.CLOCK_ROOT20.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT21.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT21.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD0_CLK} +- {id: CCM.CLOCK_ROOT22.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT22.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD2_CLK} +- {id: CCM.CLOCK_ROOT23.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT23.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT24.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT24.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '6', locked: true} +- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT27.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT27.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT28.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT28.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT29.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT29.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT30.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT30.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT31.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT31.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT32.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT32.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT33.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT33.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT34.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT34.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT35.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT35.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT36.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT36.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT37.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT37.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT38.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT38.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD1_CLK} +- {id: CCM.CLOCK_ROOT39.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT39.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT40.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT40.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT41.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT41.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK} +- {id: CCM.CLOCK_ROOT42.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD2_CLK} +- {id: CCM.CLOCK_ROOT43.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT43.MUX.sel, value: ANADIG_PLL.SYS_PLL1_CLK} +- {id: CCM.CLOCK_ROOT44.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT44.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT45.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT45.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT46.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT46.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT47.DIV.scale, value: '5', locked: true} +- {id: CCM.CLOCK_ROOT47.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT48.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT48.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT49.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT49.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT5.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT5.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT50.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT50.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK} +- {id: CCM.CLOCK_ROOT51.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT51.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT52.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT52.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT53.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT53.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT54.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT54.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT55.DIV.scale, value: '10', locked: true} +- {id: CCM.CLOCK_ROOT55.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV2_CLK} +- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT65.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT65.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT66.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT66.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT67.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT67.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT69.DIV.scale, value: '12', locked: true} +- {id: CCM.CLOCK_ROOT69.MUX.sel, value: ANADIG_PLL.PLL_AUDIO_CLK} +- {id: CCM.CLOCK_ROOT7.DIV.scale, value: '240', locked: true} +- {id: CCM.CLOCK_ROOT7.MUX.sel, value: ANADIG_OSC.OSC_24M} +- {id: CCM.CLOCK_ROOT70.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT70.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT71.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT71.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT72.DIV.scale, value: '3', locked: true} +- {id: CCM.CLOCK_ROOT72.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +- {id: CCM.CLOCK_ROOT73.DIV.scale, value: '4', locked: true} +- {id: CCM.CLOCK_ROOT73.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK} +- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240', locked: true} +- {id: CCM.CLOCK_ROOT8.MUX.sel, value: ANADIG_OSC.OSC_24M} +- {id: CCM.CLOCK_ROOT9.DIV.scale, value: '2', locked: true} +- {id: CCM.CLOCK_ROOT9.MUX.sel, value: ANADIG_PLL.SYS_PLL3_DIV2_CLK} +sources: +- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.ECAT_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT0_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT1_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT2_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT3_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.NETC_PORT4_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} +- {id: BLK_CTRL_WAKEUPMIX.SAI1_MCLK_EXT.outFreq, value: 100 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI2_MCLK_EXT.outFreq, value: 200 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI3_MCLK_EXT.outFreq, value: 300 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SAI4_MCLK_EXT.outFreq, value: 400 kHz} +- {id: BLK_CTRL_WAKEUPMIX.SPDIF_CLK_EXT.outFreq, value: 2 MHz} +- {id: BLK_CTRL_WAKEUPMIX.TMR_1588_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { + .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .loopDivider = 132, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + }; + +const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = { + .pllDiv2En = 1, /* Enable Sys Pll1 divide-by-2 clock or not */ + .pllDiv5En = 1, /* Enable Sys Pll1 divide-by-5 clock or not */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = { + .mfd = 268435455, /* Denominator of spread spectrum */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + clock_root_config_t rootCfg = {0}; + + /* Init OSC RC 400M */ + CLOCK_OSC_EnableOscRc400M(); + + /* Switch both core to OscRC400M first */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc400M; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + +#if (__CORTEX_M == 33) + /* When FlexSPI2 is used, CM33 root clock must be higher than 1/4 + of FlexSPI2 root clock, so set it to OSC RC 400M(but not OSC RC 24M) + firstly as common setting */ + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxOscRc400M; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + +#if (__CORTEX_M == 7) + DCDC_SetVoltage(kDCDC_CORE0, kDCDC_1P0Target1P1V); + DCDC_SetVoltage(kDCDC_CORE1, kDCDC_1P0Target1P1V); + /* FBB need to be enabled in OverDrive(OD) mode */ + PMU_EnableFBB(ANADIG_PMU, true); +#endif + + /* Config CLK_1M */ + CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); + + /* Init OSC RC 24M */ + CLOCK_OSC_EnableOscRc24M(true); + + /* Config OSC 24M */ + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); + /* Wait for 24M OSC to be stable. */ + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) + { + } + + /* Call function BOARD_FlexspiClockSafeConfig() to move FlexSPI clock to a stable clock source to avoid + instruction/data fetch issue when updating PLL if XIP(execute code on FLEXSPI memory). */ + BOARD_FlexspiClockSafeConfig(); + + /* Init Arm Pll. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + + /* Init Sys Pll1. */ + CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN); + +#ifndef USE_SDRAM + /* Init Sys Pll2. */ + CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN); + /* Init System Pll2 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); +#endif + /* Init System Pll2 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); + /* Init System Pll2 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + /* Init System Pll2 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); + +#ifndef USE_HYPERRAM + /* Init Sys Pll3. */ + CLOCK_InitSysPll3(); +#endif + /* Init System Pll3 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 22); + /* Init System Pll3 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 33); +#ifndef USE_HYPERRAM + /* Init System Pll3 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 22); +#endif + /* Init System Pll3 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 18); + + /* Bypass Audio Pll. */ + CLOCK_SetPllBypass(kCLOCK_PllAudio, true); + /* DeInit Audio Pll. */ + CLOCK_DeinitAudioPll(); + + /* Module clock root configurations. */ + /* Configure M7 using ARM_PLL_CLK */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + + /* Configure M33 using SYS_PLL3_CLK */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M33, &rootCfg); +#endif + + /* Configure EDGELOCK using OSC_RC_400M */ + EdgeLock_SetClock(kCLOCK_EDGELOCK_ClockRoot_MuxOscRc400M, 2); + + /* Configure BUS_AON using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_AON_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Aon, &rootCfg); + + /* Configure BUS_WAKEUP using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_BUS_WAKEUP_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Wakeup, &rootCfg); + + /* Configure WAKEUP_AXI using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_WAKEUP_AXI_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Wakeup_Axi, &rootCfg); + + /* Configure SWO_TRACE using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_SWO_TRACE_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Swo_Trace, &rootCfg); + + /* Configure M33_SYSTICK using OSC_24M */ +#if (__CORTEX_M == 33) + rootCfg.mux = kCLOCK_M33_SYSTICK_ClockRoot_MuxOsc24MOut; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M33_Systick, &rootCfg); +#endif + + /* Configure M7_SYSTICK using OSC_24M */ +#if (__CORTEX_M == 7) + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + + /* Configure FLEXIO1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg); + + /* Configure FLEXIO2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); + + /* Configure LPIT3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPIT3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lpit3, &rootCfg); + + /* Configure LPTIMER1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer1, &rootCfg); + + /* Configure LPTIMER2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer2, &rootCfg); + + /* Configure LPTIMER3 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPTIMER3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Lptimer3, &rootCfg); + + /* Configure TPM2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm2, &rootCfg); + + /* Configure TPM4 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM4_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm4, &rootCfg); + + /* Configure TPM5 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM5_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm5, &rootCfg); + + /* Configure TPM6 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_TPM6_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Tpm6, &rootCfg); + + /* Configure GPT1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); + + /* Configure GPT2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg); + + /* Configure FLEXSPI1 using SYS_PLL3_PFD0_CLK */ + BOARD_SetFlexspiClock(FLEXSPI1, kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0, 3U); + + /* Configure FLEXSPI2 using SYS_PLL3_PFD2_CLK */ +#ifndef USE_HYPERRAM + BOARD_SetFlexspiClock(FLEXSPI2, kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd2, 2U); +#endif + + /* Configure FLEXSPI_SLV using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_FLEXSPI_SLV_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi_Slv, &rootCfg); + + /* Configure CAN1 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); + + /* Configure CAN2 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg); + + /* Configure CAN3 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxSysPll3Out; + rootCfg.div = 6; + CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); + + /* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0102, &rootCfg); + + /* Configure LPUART0304 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0304_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0304, &rootCfg); + + /* Configure LPUART0506 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0506_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0506, &rootCfg); + + /* Configure LPUART0708 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0708_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0708, &rootCfg); + + /* Configure LPUART0910 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART0910_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart0910, &rootCfg); + + /* Configure LPUART1112 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPUART1112_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart1112, &rootCfg); + + /* Configure LPI2C0102 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0102_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0102, &rootCfg); + + /* Configure LPI2C0304 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0304_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0304, &rootCfg); + + /* Configure LPI2C0506 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_LPI2C0506_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg); + + /* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg); + + /* Configure LPSPI0304 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0304, &rootCfg); + + /* Configure LPSPI0506 using SYS_PLL3_PFD1_CLK */ + rootCfg.mux = kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi0506, &rootCfg); + + /* Configure I3C1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_I3C1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_I3c1, &rootCfg); + + /* Configure I3C2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_I3C2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_I3c2, &rootCfg); + + /* Configure USDHC1 using SYS_PLL2_PFD2_CLK */ + rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + + /* Configure USDHC2 using SYS_PLL2_PFD2_CLK */ + rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); + + /* Configure SEMC using SYS_PLL1_CLK */ +#ifndef USE_SDRAM + rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll1Out; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg); +#endif + + /* Configure ADC1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); + + /* Configure ADC2 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg); + + /* Configure ACMP using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); + + /* Configure ECAT using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_ECAT_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 5; + CLOCK_SetRootClock(kCLOCK_Root_Ecat, &rootCfg); + + /* Configure ENET using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_ENET_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Enet, &rootCfg); + + /* Configure TMR_1588 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_TMR_1588_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Tmr_1588, &rootCfg); + + /* Configure NETC using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_NETC_ClockRoot_MuxSysPll3Pfd3; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Netc, &rootCfg); + + /* Configure MAC0 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC0_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Mac0, &rootCfg); + + /* Configure MAC1 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC1_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac1, &rootCfg); + + /* Configure MAC2 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC2_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac2, &rootCfg); + + /* Configure MAC3 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC3_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Mac3, &rootCfg); + + /* Configure MAC4 using SYS_PLL1_DIV2_CLK */ + rootCfg.mux = kCLOCK_MAC4_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Mac4, &rootCfg); + + /* Configure SAI1 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg); + + /* Configure SAI2 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg); + + /* Configure SAI3 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg); + + /* Configure SAI4 using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg); + + /* Configure SPDIF using PLL_AUDIO_CLK */ + rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut; + rootCfg.div = 12; + CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg); + + /* Configure ASRC using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg); + + /* Configure MIC using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg); + + /* Configure CKO1 using SYS_PLL3_DIV2_CLK */ + rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); + + /* Configure CKO2 using SYS_PLL1_DIV5_CLK */ + rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxSysPll1Div5; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); + + /* Set SAI MCLK clock source. */ + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI2MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI3MClk3Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk1Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk2Sel, 0); + BLK_CTRL_SetSaiMClkClockSource(BLK_CTRL_WAKEUPMIX, kBLK_CTRL_SAI4MClk3Sel, 0); + + /* Set ECAT PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR0_MASK; + BLK_CTRL_WAKEUPMIX->ECAT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_ECAT_MISC_CFG_RMII_REF_CLK_DIR1_MASK; + + /* Set NETC PORT Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT1_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT2_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT3_RMII_REF_CLK_DIR_MASK; + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG &= ~BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK; + + /* Set TMR 1588 Ref clock source. */ + BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |= BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_TMR_EXT_CLK_SEL_MASK; + +#if (__CORTEX_M == 7) + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7); +#else + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M33); +#endif +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.h new file mode 100644 index 00000000000..80bb10092db --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/clock_config.h @@ -0,0 +1,183 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if __CORTEX_M == 7 + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 792000000UL /*!< CM7 Core clock frequency: 792000000Hz */ +#else + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 240000000UL /*!< CM33 Core clock frequency: 240000000Hz */ +#endif + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 240000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */ +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 80000000UL /* Clock consumers of ADC1_CLK_ROOT output : ADC1 */ +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 80000000UL /* Clock consumers of ADC2_CLK_ROOT output : ADC2 */ +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 792000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 240000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */ +#define BOARD_BOOTCLOCKRUN_BUS_AON_CLK_ROOT 132000000UL /* Clock consumers of BUS_AON_CLK_ROOT output : CAN1, CAN3, I3C1, IOMUXC_AON, LPI2C1, LPI2C2, LPIT1, LPSPI1, LPSPI2, LPTMR1, LPUART1, LPUART2, LPUART7, LPUART8, MU2_MUA, MU2_MUB, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, SAI1, SEMA1, TPM1, TPM2, TSTMR1_TSTMRA */ +#define BOARD_BOOTCLOCKRUN_BUS_WAKEUP_CLK_ROOT 132000000UL /* Clock consumers of BUS_WAKEUP_CLK_ROOT output : ADC1, ADC2, AOI1, AOI2, AOI3, AOI4, CAN2, CMP1, CMP2, CMP3, CMP4, DAC, EQDC1, EQDC2, EQDC3, EQDC4, EWM, FLEXIO1, FLEXIO2, I3C2, IOMUXC, KPP, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPIT2, LPIT3, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPTMR2, LPTMR3, LPUART10, LPUART11, LPUART12, LPUART3, LPUART4, LPUART5, LPUART6, LPUART9, MECC1, MECC2, MU1_MUA, MU1_MUB, PDM, PWM1, PWM2, PWM3, PWM4, RGPIO2, RGPIO3, RGPIO4, RGPIO5, RGPIO6, RTWDOG3, SAI2, SAI3, SAI4, SEMA2, SINC1, SINC2, SINC3, SPDIF, TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8, TPM3, TPM4, TPM5, TPM6, TSTMR2_TSTMRA, USBPHY1, USBPHY2, USDHC1, USDHC2, XBAR1, XBAR2, XBAR3 */ +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 80000000UL /* Clock consumers of CAN1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 80000000UL /* Clock consumers of CAN2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 80000000UL /* Clock consumers of CAN3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO1_CLK_ROOT 80000000UL /* Clock consumers of CCM_CKO1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CCM_CKO2_CLK_ROOT 50000000UL /* Clock consumers of CCM_CKO2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ECAT_CLK_ROOT 100000000UL /* Clock consumers of ECAT_CLK_ROOT output : ECAT */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT0_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ECAT_PORT1_REF_CLK 50000000UL /* Clock consumers of ECAT_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_EDGELOCK_CLK_ROOT 200000000UL /* Clock consumers of EDGELOCK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_REFCLK_ROOT 125000000UL /* Clock consumers of ENET_REFCLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 120000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 48000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_SLV_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_SLV_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 240000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 240000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_I3C1_CLK_ROOT 24000000UL /* Clock consumers of I3C1_CLK_ROOT output : I3C1 */ +#define BOARD_BOOTCLOCKRUN_I3C2_CLK_ROOT 24000000UL /* Clock consumers of I3C2_CLK_ROOT output : I3C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0102_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0102_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0304_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0304_CLK_ROOT output : LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPI2C0506_CLK_ROOT 60000000UL /* Clock consumers of LPI2C0506_CLK_ROOT output : LPI2C5, LPI2C6 */ +#define BOARD_BOOTCLOCKRUN_LPIT3_CLK_ROOT 80000000UL /* Clock consumers of LPIT3_CLK_ROOT output : LPIT3 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0102_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0102_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0304_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0304_CLK_ROOT output : LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI0506_CLK_ROOT 130909090UL /* Clock consumers of LPSPI0506_CLK_ROOT output : LPSPI5, LPSPI6 */ +#define BOARD_BOOTCLOCKRUN_LPTMR1_CLK_ROOT 80000000UL /* Clock consumers of LPTMR1_CLK_ROOT output : LPTMR1 */ +#define BOARD_BOOTCLOCKRUN_LPTMR2_CLK_ROOT 80000000UL /* Clock consumers of LPTMR2_CLK_ROOT output : LPTMR2 */ +#define BOARD_BOOTCLOCKRUN_LPTMR3_CLK_ROOT 80000000UL /* Clock consumers of LPTMR3_CLK_ROOT output : LPTMR3 */ +#define BOARD_BOOTCLOCKRUN_LPUART0102_CLK_ROOT 24000000UL /* Clock consumers of LPUART0102_CLK_ROOT output : LPUART1, LPUART2 */ +#define BOARD_BOOTCLOCKRUN_LPUART0304_CLK_ROOT 24000000UL /* Clock consumers of LPUART0304_CLK_ROOT output : LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_LPUART0506_CLK_ROOT 24000000UL /* Clock consumers of LPUART0506_CLK_ROOT output : LPUART5, LPUART6 */ +#define BOARD_BOOTCLOCKRUN_LPUART0708_CLK_ROOT 24000000UL /* Clock consumers of LPUART0708_CLK_ROOT output : LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_LPUART0910_CLK_ROOT 24000000UL /* Clock consumers of LPUART0910_CLK_ROOT output : LPUART10, LPUART9 */ +#define BOARD_BOOTCLOCKRUN_LPUART1112_CLK_ROOT 24000000UL /* Clock consumers of LPUART1112_CLK_ROOT output : LPUART11, LPUART12 */ +#define BOARD_BOOTCLOCKRUN_M33_CLK_ROOT 240000000UL /* Clock consumers of M33_CLK_ROOT output : ARM, DMA3, FLEXSPI2, RGPIO1, SysTick0 */ +#define BOARD_BOOTCLOCKRUN_M33_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M33_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 792000000UL /* Clock consumers of M7_CLK_ROOT output : ARM, SysTick1 */ +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_MAC0_CLK_ROOT 50000000UL /* Clock consumers of MAC0_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC1_CLK_ROOT 125000000UL /* Clock consumers of MAC1_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC2_CLK_ROOT 125000000UL /* Clock consumers of MAC2_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC3_CLK_ROOT 125000000UL /* Clock consumers of MAC3_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MAC4_CLK_ROOT 50000000UL /* Clock consumers of MAC4_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 80000000UL /* Clock consumers of MIC_CLK_ROOT output : PDM, SPDIF */ +#define BOARD_BOOTCLOCKRUN_NETC_CLK_ROOT 240000000UL /* Clock consumers of NETC_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT0_REF_CLK 50000000UL /* Clock consumers of NETC_PORT0_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT1_REF_CLK 50000000UL /* Clock consumers of NETC_PORT1_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT2_REF_CLK 50000000UL /* Clock consumers of NETC_PORT2_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT3_REF_CLK 50000000UL /* Clock consumers of NETC_PORT3_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_NETC_PORT4_REF_CLK 50000000UL /* Clock consumers of NETC_PORT4_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : CAN1, CAN2, CAN3, DAC, GPT1, GPT2, SPDIF, TMPSNS */ +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : CMP1, CMP2, CMP3, CMP4, EWM, GPT1, GPT2, KPP, LPTMR1, LPTMR2, LPTMR3, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_24M 24000000UL /* Clock consumers of OSC_RC_24M output : DCDC, EWM, RTWDOG1, RTWDOG2, RTWDOG3, RTWDOG4, RTWDOG5 */ +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 0UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 0UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 0UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 0UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 0UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 0UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 0UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 0UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 0UL /* Clock consumers of SAI4_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 0UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK3 0UL /* Clock consumers of SAI4_MCLK3 output : SAI4 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 200000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 0UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SWO_TRACE_CLK_ROOT 80000000UL /* Clock consumers of SWO_TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 1000000000UL /* Clock consumers of SYS_PLL1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 500000000UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 200000000UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 261818181UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 480000000UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_CLK_ROOT 240000000UL /* Clock consumers of TMR_1588_CLK_ROOT output : NETC */ +#define BOARD_BOOTCLOCKRUN_TMR_1588_REF_CLK 240000000UL /* Clock consumers of TMR_1588_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_TPM2_CLK_ROOT 80000000UL /* Clock consumers of TPM2_CLK_ROOT output : TPM2 */ +#define BOARD_BOOTCLOCKRUN_TPM4_CLK_ROOT 80000000UL /* Clock consumers of TPM4_CLK_ROOT output : TPM4 */ +#define BOARD_BOOTCLOCKRUN_TPM5_CLK_ROOT 80000000UL /* Clock consumers of TPM5_CLK_ROOT output : TPM5 */ +#define BOARD_BOOTCLOCKRUN_TPM6_CLK_ROOT 80000000UL /* Clock consumers of TPM6_CLK_ROOT output : TPM6 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 396000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ +#define BOARD_BOOTCLOCKRUN_WAKEUP_AXI_CLK_ROOT 240000000UL /* Clock consumers of WAKEUP_AXI_CLK_ROOT output : DMA4, FLEXSPI1, IEE, MECC1, MECC2, USB_OTG1, USB_OTG2, USDHC1, USDHC2 */ + + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c new file mode 100644 index 00000000000..ff39c120f77 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.c @@ -0,0 +1,82 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v15.0 +processor: MIMXRT1189xxxxx +package_id: MIMXRT1189CVM8C +mcu_data: ksdk2_0 +processor_version: 0.15.9 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33, enableClock: 'true'} +- pin_list: + - {pin_num: A5, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AON_09, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, + slew_rate: Slow} + - {pin_num: B1, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AON_08, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, open_drain: Disable, drive_strength: High, + slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins, assigned for the Cortex-M33 core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h new file mode 100644 index 00000000000..cc4b717363b --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/MCUX_Config/pin_mux.h @@ -0,0 +1,51 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M33 */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript new file mode 100644 index 00000000000..81007a0eebc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/SConscript @@ -0,0 +1,27 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +MCUX_Config/clock_config.c +MCUX_Config/pin_mux.c +""") + +CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports'] +CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm7', 'MIMXRT1189_cm7_SERIES', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1', 'ARM_MATH_CM7'] + +if rtconfig.PLATFORM in ['gcc']: + CPPDEFINES += ['__STARTUP_INITIALIZE_RAMFUNCTION'] + +if rtconfig.PLATFORM in ['armcc', 'armclang']: + # CPPDEFINES += ['SDK_DEBUGCONSOLE'] + CPPDEFINES += ['NDEBUG'] + +if rtconfig.PLATFORM in ['iccarm']: + CPPDEFINES += ['NDEBUG'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c new file mode 100644 index 00000000000..0c4db043d11 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.c @@ -0,0 +1,297 @@ +/* + * Copyright 2021-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include "board.h" +#include "pin_mux.h" +#include "fsl_iomuxc.h" +#include "fsl_rgpio.h" +#include "fsl_cache.h" + +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +/* MPU configuration. */ +void BOARD_ConfigMPU(void) +{ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_aux is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_aux$$Base[]; + uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base; + uint32_t nonCacheSize = ((uint32_t)Image$$RW_m_ncache_aux$$Base) - nonCacheStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION); + uint32_t nonCacheSize = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START; + uint32_t nonCacheSize = (uint32_t)__NCACHE_REGION_SIZE; +#endif +#if defined(__USE_SHMEM) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; + /* RPMSG_SH_MEM_aux is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ + extern uint32_t Image$$RPMSG_SH_MEM_aux$$Base[]; + uint32_t rpmsgShmemStart = (uint32_t)Image$$RPMSG_SH_MEM$$Base; + uint32_t rpmsgShmemSize = ((uint32_t)Image$$RPMSG_SH_MEM_aux$$Base) - rpmsgShmemStart; +#elif defined(__MCUXPRESSO) + extern uint32_t __base_SHMEM_REGION; + extern uint32_t __top_SHMEM_REGION; + uint32_t rpmsgShmemStart = (uint32_t)(&__base_SHMEM_REGION); + uint32_t rpmsgShmemSize = (uint32_t)(&__top_SHMEM_REGION) - rpmsgShmemStart; +#elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __RPMSG_SH_MEM_START[]; + extern uint32_t __RPMSG_SH_MEM_SIZE[]; + uint32_t rpmsgShmemStart = (uint32_t)__RPMSG_SH_MEM_START; + uint32_t rpmsgShmemSize = (uint32_t)__RPMSG_SH_MEM_SIZE; +#endif +#endif + volatile uint32_t i; + + /* Disable I cache and D cache */ + L1CACHE_DisableICache(); + L1CACHE_DisableDCache(); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* clang-format off */ + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outer cache + * policy, please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in mpu_armv7.h. + */ + + /* clang-format on */ + + /* + * Add default region to deny access to whole address space to workaround speculative prefetch. + * Refer to Arm errata 1013783-B for more details. + */ + + /* Region 0 setting: Instruction access disabled, No data access permission. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2GB); + + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ /*ITCM*/ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ /*DTCM*/ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + MPU->RBAR = ARM_MPU_RBAR(6, 0x20480000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM1*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB); +#else + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM1*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); +#endif + + MPU->RBAR = ARM_MPU_RBAR(7, 0x20500000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write through */ /*OCRAM2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_256KB); +#else + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ /*OCRAM2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); +#endif + +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI1*/ + MPU->RBAR = ARM_MPU_RBAR(8, 0x28000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB); +#endif + +#if defined(USE_HYPERRAM) + MPU->RBAR = ARM_MPU_RBAR(9, 0x04000000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write through. */ /*FSPI2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_8MB); +#else + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back. */ /*FSPI2*/ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB); +#endif +#endif + +#if defined(USE_SDRAM) + MPU->RBAR = ARM_MPU_RBAR(10, 0x80000000U); +#if defined(CACHE_MODE_WRITE_THROUGH) + /* Region 10 setting: Memory with Normal type, not shareable, outer/inner write through */ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB); +#else + /* Region 10 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); +#endif +#endif + + i = 0; + while ((nonCacheSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % nonCacheSize)); + assert(nonCacheSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 11 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(11, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } + +#if defined(__USE_SHMEM) + i = 0; + while ((rpmsgShmemSize >> i) > 0x1U) + { + i++; + } + + if (i != 0) + { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t)(1 << i)); + assert(i >= 5); + + /* Region 12 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(12, rpmsgShmemStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } +#endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enable I cache and D cache */ + L1CACHE_EnableDCache(); + L1CACHE_EnableICache(); +} + +/* This is the timer interrupt service routine. */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void imxrt_uart_pins_init(void) +{ +#ifdef BSP_USING_LPUART1 + CLOCK_EnableClock(kCLOCK_Iomuxc2); /* Turn on LPCG: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 is configured as LPUART1_TX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 is configured as LPUART1_RX */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_08_LPUART1_TX, /* GPIO_AON_08 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AON_09_LPUART1_RX, /* GPIO_AON_09 PAD functional properties : */ + 0x02U); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: high driver + Pull / Keep Select Field: Pull Disable, Highz + Pull Up / Down Config. Field: Weak pull down + Open Drain Field: Disabled */ +#endif +} + +void rt_hw_board_init() +{ + BOARD_ConfigMPU(); + BOARD_InitPins(); + BOARD_BootClockRUN(); + + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + +#ifdef BSP_USING_LPUART + imxrt_uart_pins_init(); +#endif + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h new file mode 100644 index 00000000000..a69a6880cae --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/board.h @@ -0,0 +1,39 @@ +/* + * Copyright 2021-2025 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "clock_config.h" +#include "pin_mux.h" +#include "fsl_common.h" +#include "fsl_rgpio.h" +#include "fsl_clock.h" + +#if defined(__ARMCC_VERSION) +extern int Image$$ARM_LIB_HEAP$$ZI$$Base; +extern int Image$$ARM_LIB_HEAP$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_END ((void*)&Image$$ARM_LIB_HEAP$$ZI$$Limit) +#elif defined(__ICCARM__) +#pragma section="HEAP" +#define HEAP_BEGIN (__section_begin("HEAP")) +#define HEAP_END (__section_end("HEAP")) +#elif defined(__GNUC__) +extern int __HeapBase; +extern int __HeapLimit; +#define HEAP_BEGIN ((void *)&__HeapBase) +#define HEAP_END ((void *)&__HeapLimit) +#endif + +/*! @brief The board flash size */ +#define BOARD_FLASH_SIZE (0x1000000U) + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/evkmimxrt1180_ram_cm7.ini b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/evkmimxrt1180_ram_cm7.ini new file mode 100644 index 00000000000..d21f38d50c8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/evkmimxrt1180_ram_cm7.ini @@ -0,0 +1,414 @@ +/* + * Copyright 2023-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +FUNC void _FLEXSPI1_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI1_WaitBusIdle(void) +{ + unsigned int reg; + reg = _RDWORD(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FLEXSPI1_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + _WDWORD(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +FUNC void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + _WDWORD(0x42A1023C, 0x17); + _WDWORD(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + _WDWORD(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + _WDWORD(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + _WDWORD(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + _WDWORD(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + _WDWORD(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + _WDWORD(0x42A10254, 0x17); +} + +FUNC void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = _RDWORD(0x425E0000); + _WDWORD(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + _WDWORD(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + _WDWORD(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + _WDWORD(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + _WDWORD(0x425E0060, 0x00004000); + + //FLEXSPI1->FLSHCR4 = 0xC3; + _WDWORD(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + _WDWORD(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + _WDWORD(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + _WDWORD(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + _WDWORD(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + _WDWORD(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + _WDWORD(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + _WDWORD(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + _WDWORD(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + _WDWORD(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + _WDWORD(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + _WDWORD(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + _WDWORD(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + _WDWORD(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + _WDWORD(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + _WDWORD(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + _WDWORD(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + _WDWORD(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + _WDWORD(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + _WDWORD(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + _WDWORD(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + _WDWORD(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + _WDWORD(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + _WDWORD(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + _WDWORD(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + _WDWORD(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + _WDWORD(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + _WDWORD(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + _WDWORD(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + _WDWORD(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + _WDWORD(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + _WDWORD(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + _WDWORD(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + _WDWORD(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + _WDWORD(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + _WDWORD(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + _WDWORD(0x425E001C, 0x01); +} + +FUNC void _FLEXSPI2_ModuleReset(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg | 0x1)); + do + { + reg = _RDWORD(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +FUNC void _FLEXSPI2_WaitBusIdle(void) +{ + unsigned int reg; + + reg = _RDWORD(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = _RDWORD(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +FUNC void _FlexSPI2_SetPinForOctalMode(void) +{ + // Config IOMUX for FlexSPI2 + _WDWORD(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + _WDWORD(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + _WDWORD(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + _WDWORD(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + _WDWORD(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + _WDWORD(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + _WDWORD(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + _WDWORD(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + _WDWORD(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + _WDWORD(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + _WDWORD(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + _WDWORD(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + _WDWORD(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + _WDWORD(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + _WDWORD(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +FUNC void _FLEXSPI2_ClockInit(void) +{ + _WDWORD(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + _WDWORD(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +FUNC void _FLEXSPI2_ModuleInit(void) +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = _RDWORD(0x445E0000); + _WDWORD(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0004, 0xFFFFFFFF); // MCR1 + _WDWORD(0x445E0008, 0x200001F7); // MCR2 + _WDWORD(0x445E000C, 0x00000078); // AHBCR prefetch enable + _WDWORD(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + _WDWORD(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + _WDWORD(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + _WDWORD(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + _WDWORD(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + _WDWORD(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + _WDWORD(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + _WDWORD(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + _WDWORD(0x445E00B8, 0x00000000); // IPRXFCR + _WDWORD(0x445E00BC, 0x00000000); // IPTXFCR + + _WDWORD(0x445E0060, 0x00000000); // FLASHA1CR0 + _WDWORD(0x445E0064, 0x00000000); // FLASHA2CR0 + _WDWORD(0x445E0068, 0x00000000); // FLASHB1CR0 + _WDWORD(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0060, 0x00002000); // FLASHA1CR0 + _WDWORD(0x445E0070, 0x00021C63); // FLASHA1CR1 + _WDWORD(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E00C0, 0x00000079); // DLLCRA + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = _RDWORD(0x445E00E8); + } while (0x3 != (reg & 0x3)); + _Sleep_(1); + // __delay(100);//100us + + _WDWORD(0x445E0000, 0xFFFF3032); // MCR0 + _WDWORD(0x445E0094, 0x000000C2); // FLASHCR4 + _WDWORD(0x445E0094, 0x000000C6); // FLASHCR4 + _WDWORD(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000002); // LUTCR + _WDWORD(0x445E0200, 0x8B1887A0); // LUT[0] + _WDWORD(0x445E0204, 0xB7078F10); // LUT[1] + _WDWORD(0x445E0208, 0x0000A704); // LUT[2] + _WDWORD(0x445E020C, 0x00000000); // LUT[3] + _WDWORD(0x445E0210, 0x8B188720); // LUT[4] + _WDWORD(0x445E0214, 0xB7078F10); // LUT[5] + _WDWORD(0x445E0218, 0x0000A304); // LUT[6] + _WDWORD(0x445E021C, 0x00000000); // LUT[7] + _WDWORD(0x445E0220, 0x8B1887E0); // LUT[8] + _WDWORD(0x445E0224, 0xB7078F10); // LUT[9] + _WDWORD(0x445E0228, 0x0000A704); // LUT[10] + _WDWORD(0x445E022C, 0x00000000); // LUT[11] + _WDWORD(0x445E0230, 0x8B188760); // LUT[12] + _WDWORD(0x445E0234, 0xA3028F10); // LUT[13] + _WDWORD(0x445E0238, 0x00000000); // LUT[14] + _WDWORD(0x445E023C, 0x00000000); // LUT[15] + _WDWORD(0x445E0240, 0x00000000); // LUT[16] + _WDWORD(0x445E0244, 0x00000000); // LUT[17] + _WDWORD(0x445E0248, 0x00000000); // LUT[18] + _WDWORD(0x445E024C, 0x00000000); // LUT[19] + _WDWORD(0x445E0018, 0x5AF05AF0); // LUTKEY + _WDWORD(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + _WDWORD(0x445E00A0, 0x00001000); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + _WDWORD(0x445E00A0, 0x00001002); // IPCR0 + _WDWORD(0x445E00A4, 0x00030002); // IPCR1 + _WDWORD(0x445E00BC, 0x00000001); // IPTXFCR + _WDWORD(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + _WDWORD(0x445E0014, 0x00000040); // INTR + _WDWORD(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = _RDWORD(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + _WDWORD(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +FUNC void Flash_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init Flash\r\n"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void HyperRAM_Init(void) +{ + printf("***************************************************\r\n"); + printf("Init HyperRAM\r\n"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + printf("***************************************************\r\n"); +} + +FUNC void ClearNVIC(void) { + printf("***************************************************\r\n"); + printf("Clear NVIC\r\n"); + printf("***************************************************\r\n"); + memset(0xE000E180, 0x40, 0xFF); + memset(0xE000E280, 0x40, 0xFF); +} + +FUNC void Setup_PC_SP(void) +{ + SP = _RDWORD(0x00000000); // Setup Stack Pointer + PC = _RDWORD(0x00000004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register +} + +FUNC void Setup (void) { + ClearNVIC(); + // Flash_Init(); + HyperRAM_Init(); + Setup_PC_SP(); +} + +FUNC void OnResetExec (void) +{ + // executes upon RESET + Setup(); +} + +Setup(); diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.icf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.icf new file mode 100644 index 00000000000..62301304f73 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.icf @@ -0,0 +1,154 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Board memory map */ +define symbol m_itcm_start = 0x00000000; +define symbol m_itcm_size = 0x00040000; + +define symbol m_dtcm_start = 0x20000000; +define symbol m_dtcm_size = 0x00040000; + +define symbol m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +define symbol m_ocram1_size = 0x0007C000; + +define symbol m_ocram2_start = 0x20500000; +define symbol m_ocram2_size = 0x00040000; + +define symbol m_sdram_start = 0x80000000; +define symbol m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_hyperram_start = 0x04000000; +define symbol m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +define symbol m_flash_start = 0x28000000; +define symbol m_flash_size = 0x01000000; + +/* General definition */ +define symbol app_image_offset = 0x0000B000; +define symbol vector_table_size = 0x00000400; +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x1000; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x4000; +} + +define symbol m_qacode_start = m_itcm_start + (isdefinedsymbol(__ram_vector_table__) ? vector_table_size : 0); +define symbol m_qacode_end = m_itcm_start + m_itcm_size - 1; +define symbol m_qadata_start = m_dtcm_start; +define symbol m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +define symbol m_ram_vector_table_start = m_itcm_start; + +/* Target specific definition, code & data allocation */ +define symbol m_code_size = m_itcm_size; +define symbol m_data_size = m_dtcm_size; +define symbol m_ncache_size = isdefinedsymbol(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +define symbol m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +define symbol m_ocram1_size_for_cm7 = isdefinedsymbol(__multicore__) ? 0x40000 : m_ocram1_size; + +define symbol m_ram_vector_table_size = isdefinedsymbol(__ram_vector_table__) ? 0 : 0; + +define symbol m_text_start = m_itcm_start; +define symbol m_text_end = m_text_start + m_code_size - 1; +define symbol m_interrupts_start = m_text_start; + +define symbol m_data_start = m_dtcm_start; +define symbol m_data_end = m_data_start + m_data_size - 1; + +define symbol m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +define symbol m_ncache_end = m_ncache_start + m_ncache_size - 1; + +define symbol m_heap_start = m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +define symbol m_heap_end = m_ncache_start - 1; + +if (isdefinedsymbol(__use_shmem__)) { + define symbol m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ + define symbol m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; +} + +/* Exported symbol definition */ +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_ram_vector_table_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = m_ram_vector_table_size; +define exported symbol __NCACHE_REGION_START = m_ncache_start; +define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1; +if (isdefinedsymbol(__use_shmem__)) { + define exported symbol rpmsg_sh_mem_start = m_rpmsg_sh_mem_start; + define exported symbol rpmsg_sh_mem_end = m_rpmsg_sh_mem_end; + define exported symbol __RPMSG_SH_MEM_START = m_rpmsg_sh_mem_start; + define exported symbol __RPMSG_SH_MEM_SIZE = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1; +} + +define exported symbol __RTT_HEAP_END = m_ocram2_start + m_ocram2_size - 1; + +/* Region definition */ +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; +define region HEAP_region = mem:[from m_heap_start to m_heap_end]; +define region QACODE_region = mem:[from m_qacode_start to m_qacode_end]; +define region QADATA_region = mem:[from m_qadata_start to m_qadata_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from m_rpmsg_sh_mem_start to m_rpmsg_sh_mem_end]; +} + +/* Block definition */ +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; + +initialize by copy { readwrite, section .textrw, section DataQuickAccess }; +do not initialize { section .noinit }; +if (isdefinedsymbol(__use_shmem__)) { + do not initialize { section rpmsg_sh_mem_section }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in TEXT_region { block QACCESS_CODE }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { block QACCESS_DATA }; +place in NCACHE_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; +if (isdefinedsymbol(__heap_noncacheable__)) { + place in NCACHE_region { last block HEAP }; +} else { + place in HEAP_region { last block HEAP }; +} +if (isdefinedsymbol(__use_shmem__)) { + place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.lds b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.lds new file mode 100644 index 00000000000..b07f7f41179 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.lds @@ -0,0 +1,330 @@ +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Board memory map */ +m_itcm_start = 0x00000000; +m_itcm_size = 0x00040000; +m_dtcm_start = 0x20000000; +m_dtcm_size = 0x00040000; +m_ocram1_start = 0x20484000; /* OCRAM1 first 16K access is blocked by TRDC */ +m_ocram1_size = 0x0007C000; +m_ocram2_start = 0x20500000; +m_ocram2_size = 0x00040000; +m_sdram_start = 0x80000000; +m_sdram_size = 0x01E00000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +m_hyperram_start = 0x04000000; +m_hyperram_size = 0x00600000; /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +m_flash_start = 0x28000000; +m_flash_size = 0x01000000; + +/* General definition */ +app_image_offset = 0x0000B000; +vector_table_size = 0x00000400; +m_qacode_start = m_itcm_start + (DEFINED(__ram_vector_table__) ? vector_table_size : 0); +m_qacode_end = m_itcm_start + m_dtcm_size - 1; +m_qadata_start = m_dtcm_start; +m_qadata_end = m_dtcm_start + m_dtcm_size - 1; +m_ram_vector_table_start = m_itcm_start; +m_stack_size = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +m_heap_size = DEFINED(__heap_size__) ? __heap_size__ : 0x4000; + +/* Target specific definition, code & data allocation */ +m_code_size = m_itcm_size - vector_table_size; +m_data_size = m_dtcm_size; +m_ncache_size = DEFINED(__multicore__) ? 0x20000 : 0x40000; /* m_ncache_size must be 2^N */ +m_shmem_size = m_ocram2_size; /* m_shmem_size must be 2^N */ + +m_ocram1_size_for_cm7 = DEFINED(__multicore__) ? 0x40000 : m_ocram1_size; + +m_ram_vector_table_size = DEFINED(__ram_vector_table__) ? 0 : 0; + +m_interrupts_start = m_itcm_start; +m_interrupts_end = m_interrupts_start + vector_table_size - 1; + +m_text_start = m_interrupts_end + 1; +m_text_end = m_text_start + m_code_size - 1; + +m_data_start = m_dtcm_start; +m_data_end = m_data_start + m_data_size - 1; + +m_ncache_start = m_ocram1_start + m_ocram1_size - m_ncache_size; /* (m_ncache_start % m_ncache_size) must be 0 */ +m_ncache_end = m_ncache_start + m_ncache_size - 1 - (DEFINED(__heap_noncacheable__) ? m_heap_size : 0); + +m_heap_start = DEFINED(__heap_noncacheable__) ? m_ncache_end + 1 : m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7; +m_heap_end = m_heap_start + m_heap_size - 1; + +m_rpmsg_sh_mem_start = m_ocram2_start; /* (m_rpmsg_sh_mem_start % m_shmem_size) must be 0 */ +m_rpmsg_sh_mem_end = m_rpmsg_sh_mem_start + m_shmem_size - 1; + +/* Exported symbol definition */ +__VECTOR_TABLE = m_interrupts_start; +__VECTOR_RAM = m_ram_vector_table_start; +__RAM_VECTOR_TABLE_SIZE_BYTES = m_ram_vector_table_size; + +__NCACHE_REGION_START = m_ncache_start; +__NCACHE_REGION_SIZE = m_ncache_size; +__RPMSG_SH_MEM_START = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_start : 0; +__RPMSG_SH_MEM_SIZE = DEFINED(__use_shmem__)? m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 : 0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts_ram (RX) : ORIGIN = m_ram_vector_table_start, LENGTH = __RAM_VECTOR_TABLE_SIZE_BYTES + m_interrupts (RX) : ORIGIN = m_interrupts_start, LENGTH = m_interrupts_end - m_interrupts_start + 1 + m_text (RX) : ORIGIN = m_text_start, LENGTH = m_text_end - m_text_start + 1 + m_data (RW) : ORIGIN = m_data_start, LENGTH = m_data_end - m_data_start + 1 + m_ncache (RW) : ORIGIN = m_ncache_start, LENGTH = m_ncache_end - m_ncache_start + 1 + m_heap (RW) : ORIGIN = m_heap_start, LENGTH = m_heap_end - m_heap_start + 1 + m_qacode (RX) : ORIGIN = m_qacode_start, LENGTH = m_qacode_end - m_qacode_start + 1 + m_qadata (RW) : ORIGIN = m_qadata_start, LENGTH = m_qadata_end - m_qadata_start + 1 + m_rpmsg (RW) : ORIGIN = m_rpmsg_sh_mem_start, LENGTH = m_rpmsg_sh_mem_end - m_rpmsg_sh_mem_start + 1 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first */ + .interrupts : + { + . = ALIGN(4); + __Vectors = .; + KEEP(*(.isr_vector)) /* Vector table and startup code */ + . = ALIGN(4); + } > m_interrupts + + .interrupts_ram : + { + . = ALIGN(4); + . += __RAM_VECTOR_TABLE_SIZE_BYTES; + . = ALIGN(4); + } > m_interrupts_ram + + /* The program code */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(CodeQuickAccess) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* RT-Thread FinSH symbol table */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + /* RT-Thread init table */ + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* RT-Thread init functions */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + + __data_flash_start = .; /* Symbol is used by startup for data initialization */ + .data : AT(__data_flash_start) + { + . = ALIGN(4); + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __ram_function_flash_start = __data_flash_start + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM code initialization */ + .ram_function : AT(__ram_function_flash_start) + { + . = ALIGN(32); + __ram_function_start__ = .; + . = ALIGN(128); + __ram_function_end__ = .; + } > m_qacode + + __noncache_data_flash_start = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__); + .ncache.init : AT(__noncache_data_flash_start) + { + . = ALIGN(4); + __noncache_data_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncache_data_end__ = .; /* create a global symbol at ncache data end */ + } > m_ncache + + .ncache : + { + . = ALIGN(4); + __noncache_bss_start__ = .; /* define a global symbol at ncache bss start */ + *(NonCacheable) + . = ALIGN(4); + __noncache_bss_end__ = .; /* define a global symbol at ncache bss end */ + } > m_ncache + + __qadata_flash_start = __noncache_data_flash_start + (__noncache_data_end__ - __noncache_data_start__); + .qadata : AT(__qadata_flash_start) + { + . = ALIGN(4); + __qadata_start__ = .; + . = ALIGN(4); + __qadata_end__ = .; + } > m_qadata + + text_data_end = __qadata_flash_start + (__qadata_end__ - __qadata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(text_data_end < text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > m_data + + .rpmsg : + { + *(.noinit.$rpmsg_sh_mem) + } > m_rpmsg + + .heap : + { + . = ALIGN(8); + __HeapBase = .; + end = .; + . += m_heap_size; + __HeapLimit = .; /* Add for _sbrk */ + } > m_heap + + .stack : + { + . = ALIGN(8); + __StackStart = .; + . += m_stack_size; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - m_stack_size; + PROVIDE(__stack = __StackTop); + PROVIDE (__stack_size = m_stack_size); + ASSERT(__StackLimit >= __StackStart, "region m_data overflowed with stack and heap") + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.scf b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.scf new file mode 100644 index 00000000000..8b6b98562ce --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/board/linker_scripts/link_ram.scf @@ -0,0 +1,178 @@ +#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c +/* +** ################################################################### +** Processors: MIMXRT1189CVM8B_cm7 +** MIMXRT1189CVM8C_cm7 +** MIMXRT1189XVM8B_cm7 +** MIMXRT1189XVM8C_cm7 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1180RM, Rev 5, 01/2024 +** Version: rev. 2.0, 2024-01-18 +** Build: b250310 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2025 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Board memory map */ + +#define m_itcm_start 0x00000000 +#define m_itcm_size 0x00040000 + +#define m_dtcm_start 0x20000000 +#define m_dtcm_size 0x00040000 + +#define m_ocram1_start 0x20484000 /* OCRAM1 first 16K access is blocked by TRDC */ +#define m_ocram1_size 0x0007C000 + +#define m_ocram2_start 0x20500000 +#define m_ocram2_size 0x00040000 + +#define m_sdram_start 0x80000000 +#define m_sdram_size 0x01E00000 /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +#define m_hyperram_start 0x04000000 +#define m_hyperram_size 0x00600000 /* Reserved 2M for CM33 usage, so size = physical memory size - 2M */ +#define m_flash_start 0x28000000 +#define m_flash_size 0x01000000 + +/* General definition */ +#define app_image_offset 0x0000B000 +#define vector_table_size 0x400 +#define m_ram_vector_table_start m_itcm_start + +#if defined(__stack_size__) + #define stack_size __stack_size__ +#else + #define stack_size 0x01000 +#endif + +#if defined(__heap_size__) + #define heap_size __heap_size__ +#else + #define heap_size 0x04000 +#endif + +/* Target specific definition, code & data allocation */ +#if defined(__ram_vector_table__) +#define m_ram_vector_table_size 0 +#else +#define m_ram_vector_table_size 0 +#endif + +#define m_qacode_start m_itcm_start + m_ram_vector_table_size +#define m_qadata_start m_dtcm_start +#define m_qacode_size 0 +#define m_qadata_size 0 + +#define m_text_size m_itcm_size +#define m_data_size m_dtcm_size +#if defined(__multicore__) +#define m_ncache_size 0x20000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 0x40000 +#else +#define m_ncache_size 0x40000 /* m_ncache_size must be 2^N */ +#define m_ocram1_size_for_cm7 m_ocram1_size +#endif + +#define m_shmem_size m_ocram2_size /* m_shmem_size must be 2^N */ + +#define m_text_start m_itcm_start +#define m_interrupts_start m_text_start +#define m_data_start m_dtcm_start +#define m_ncache_start m_ocram1_start + m_ocram1_size - m_ncache_size +#define m_heap_start m_ocram1_start + m_ocram1_size - m_ocram1_size_for_cm7 + +#if defined(__use_shmem__) +#define m_shmem_start m_ocram2_start +#endif + +; load region +LR_m_text m_text_start m_text_size +{ + ; load address = execution address + VECTOR_ROM m_interrupts_start FIXED vector_table_size + { + * (.isr_vector,+FIRST) + } + + VECTOR_RAM m_ram_vector_table_start EMPTY m_ram_vector_table_size + { + } + + ; load address = execution address + ER_m_text m_text_start + vector_table_size FIXED m_text_size - vector_table_size + { + * (InRoot$$Sections) + .ANY (+RO) + .ANY (CodeQuickAccess) + } + + ER_m_QuickAccessCode m_qacode_start EMPTY m_qacode_size + { + } + + ER_m_QuickAccessData m_qadata_start EMPTY m_qadata_size + { + } + + RW_m_data m_data_start m_data_size-stack_size + { + .ANY (+RW +ZI) + .ANY (DataQuickAccess) + } + + ; ncache data + RW_m_ncache m_ncache_start m_ncache_size + { + .ANY (NonCacheable.init) + .ANY (.bss.NonCacheable) + } + +#if defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP +0 ALIGN 0x100 EMPTY heap_size + { + } +#endif + + ; Empty region added for MPU configuration + RW_m_ncache_aux m_ncache_start + m_ncache_size EMPTY 0 + { + } + +#if defined(__use_shmem__) + ; shared memory data + RPMSG_SH_MEM m_shmem_start m_shmem_size + { + .ANY (rpmsg_sh_mem_section) + } + + ; Empty region added for MPU configuration + RPMSG_SH_MEM_aux m_shmem_start + m_shmem_size EMPTY 0 + { + } +#endif + +#if !defined(__heap_noncacheable__) + ; Heap region growing up + ARM_LIB_HEAP m_heap_start EMPTY heap_size + { + } +#endif + + ; Stack region growing down + ARM_LIB_STACK m_data_start+m_data_size EMPTY -stack_size + { + } +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180.mac b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180.mac new file mode 100644 index 00000000000..8b21a75c9e9 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180.mac @@ -0,0 +1,430 @@ +/* + * Copyright 2023-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +_FLEXSPI1_ModuleReset() +{ + __var reg; + + reg = __readMemory32(0x425E0000, "Memory"); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = __readMemory32(0x425E0000, "Memory"); + __writeMemory32((reg | 0x1), 0x425E0000, "Memory"); + do + { + reg = __readMemory32(0x425E0000, "Memory"); + } while ((reg & 0x1) != 0); + } +} + +_FLEXSPI1_WaitBusIdle() +{ + __var reg; + + reg = __readMemory32(0x425E0000, "Memory"); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = __readMemory32(0x425E00E0, "Memory"); + } while ((reg & 0x3) != 0x3); + } +} + +_FLEXSPI1_ClockInit() +{ + __writeMemory32(0x0, 0x54484350, "Memory"); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + __writeMemory32(0x103, 0x54450A80, "Memory"); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +_FLEXSPI1_SetPinForQuadMode() { + // Set 4 Pin Mode for JLink + __writeMemory32(0x17, 0x42A1023C, "Memory"); // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + __writeMemory32(0x1, 0x42A10544, "Memory"); + __writeMemory32(0x17, 0x42A10240, "Memory"); // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + __writeMemory32(0x17, 0x42A10244, "Memory"); // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + __writeMemory32(0x17, 0x42A10248, "Memory"); // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + __writeMemory32(0x17, 0x42A1024C, "Memory"); // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + __writeMemory32(0x17, 0x42A10250, "Memory"); // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + __writeMemory32(0x17, 0x42A10254, "Memory"); // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 +} + +_FLEXSPI1_ModuleInit() { + + __var reg; + + reg = __readMemory32(0x425E0000, "Memory"); + __writeMemory32((reg & 0xFFFFFFFD), 0x425E0000, "Memory"); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + __writeMemory32(0xFFFF8010, 0x425E0000, "Memory"); + //FLEXSPI1->MCR2 = 0x200001F7; + __writeMemory32(0x200001F7, 0x425E0008, "Memory"); + //FLEXSPI1->AHBCR = 0x78; + __writeMemory32(0x78, 0x425E000C, "Memory"); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + __writeMemory32(0x00004000, 0x425E0060, "Memory"); + + //FLEXSPI1->FLSHCR4 = 0xC3; + __writeMemory32(0xC3, 0x425E0094, "Memory"); + //FLEXSPI1->IPRXFCR = 0x1C; + __writeMemory32(0x1C, 0x425E00B8, "Memory"); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + __writeMemory32(0x5AF05AF0, 0x425E0018, "Memory"); + //FLEXSPI1->LUTCR = 0x02; + __writeMemory32(0x02, 0x425E001C, "Memory"); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + __writeMemory32(0x0A1804EB, 0x425E0200, "Memory"); + //FLEXSPI1->LUT[1] = 0x26043206; + __writeMemory32(0x26043206, 0x425E0204, "Memory"); + //FLEXSPI1->LUT[2] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0208, "Memory"); + //FLEXSPI1->LUT[3] = 0x00000000; + __writeMemory32(0x00000000, 0x425E020C, "Memory"); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + __writeMemory32(0x00000406, 0x425E0210, "Memory"); + //FLEXSPI1->LUT[5] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0214, "Memory"); + //FLEXSPI1->LUT[6] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0218, "Memory"); + //FLEXSPI1->LUT[7] = 0x00000000; + __writeMemory32(0x00000000, 0x425E021C, "Memory"); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + __writeMemory32(0x20040401, 0x425E0220, "Memory"); + //FLEXSPI1->LUT[9] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0224, "Memory"); + //FLEXSPI1->LUT[10] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0228, "Memory"); + //FLEXSPI1->LUT[11] = 0x00000000; + __writeMemory32(0x00000000, 0x425E022C, "Memory"); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + __writeMemory32(0x24040405, 0x425E0230, "Memory"); + //FLEXSPI1->LUT[13] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0234, "Memory"); + //FLEXSPI1->LUT[14] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0238, "Memory"); + //FLEXSPI1->LUT[15] = 0x00000000; + __writeMemory32(0x00000000, 0x425E023C, "Memory"); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + __writeMemory32(0x00000404, 0x425E0240, "Memory"); + //FLEXSPI1->LUT[17] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0244, "Memory"); + //FLEXSPI1->LUT[18] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0248, "Memory"); + //FLEXSPI1->LUT[19] = 0x00000000; + __writeMemory32(0x00000000, 0x425E024C, "Memory"); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + __writeMemory32(0x20040431, 0x425E0250, "Memory"); + //FLEXSPI1->LUT[21] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0254, "Memory"); + //FLEXSPI1->LUT[22] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0258, "Memory"); + //FLEXSPI1->LUT[23] = 0x00000000; + __writeMemory32(0x00000000, 0x425E025C, "Memory"); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + __writeMemory32(0x24040435, 0x425E0260, "Memory"); + //FLEXSPI1->LUT[25] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0264, "Memory"); + //FLEXSPI1->LUT[26] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0268, "Memory"); + //FLEXSPI1->LUT[27] = 0x00000000; + __writeMemory32(0x00000000, 0x425E026C, "Memory"); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + __writeMemory32(0x00000450, 0x425E0270, "Memory"); + //FLEXSPI1->LUT[29] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0274, "Memory"); + //FLEXSPI1->LUT[30] = 0x00000000; + __writeMemory32(0x00000000, 0x425E0278, "Memory"); + //FLEXSPI1->LUT[31] = 0x00000000; + __writeMemory32(0x00000000, 0x425E027C, "Memory"); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + __writeMemory32(0x5AF05AF0, 0x425E0018, "Memory"); + //FLEXSPI1->LUTCR = 0x01; + __writeMemory32(0x01, 0x425E001C, "Memory"); +} + +_FLEXSPI2_ModuleReset() +{ + __var reg; + + reg = __readMemory32(0x445E0000, "Memory"); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = __readMemory32(0x445E0000, "Memory"); + __writeMemory32((reg | 0x1), 0x445E0000, "Memory"); + do + { + reg = __readMemory32(0x445E0000, "Memory"); + } while ((reg & 0x1) != 0); + } +} + +_FLEXSPI2_WaitBusIdle() +{ + __var reg; + + reg = __readMemory32(0x445E0000, "Memory"); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = __readMemory32(0x445E00E0, "Memory"); + } while ((reg & 0x3) != 0x3); + } +} + +_FlexSPI2_SetPinForOctalMode() +{ + // Config IOMUX for HyperRAM + __writeMemory32(0x00000013, 0x42A10088, "Memory");// FLEXSPI2_B_DATA03 + __writeMemory32(0x00000013, 0x42A1008C, "Memory");// FLEXSPI2_B_DATA02 + __writeMemory32(0x00000013, 0x42A10090, "Memory");// FLEXSPI2_B_DATA01 + __writeMemory32(0x00000013, 0x42A10094, "Memory");// FLEXSPI2_B_DATA00 + __writeMemory32(0x00000013, 0x42A1009C, "Memory");// FLEXSPI2_A_DATA00 + __writeMemory32(0x00000013, 0x42A100A0, "Memory");// FLEXSPI2_A_DATA01 + __writeMemory32(0x00000013, 0x42A100A4, "Memory");// FLEXSPI2_A_DATA02 + __writeMemory32(0x00000013, 0x42A100A8, "Memory");// FLEXSPI2_A_DATA03 + __writeMemory32(0x00000013, 0x42A100AC, "Memory");// FLEXSPI2_A_SS0_B + __writeMemory32(0x00000013, 0x42A100B0, "Memory");// FLEXSPI2_A_DQS + __writeMemory32(0x00000013, 0x42A100B4, "Memory");// FLEXSPI2_A_SCLK + + //The input daisy!! + __writeMemory32(0x00000001, 0x42A10594, "Memory");// FLEXSPI2_B_DATA03 + __writeMemory32(0x00000001, 0x42A10590, "Memory");// FLEXSPI2_B_DATA02 + __writeMemory32(0x00000001, 0x42A1058C, "Memory");// FLEXSPI2_B_DATA01 + __writeMemory32(0x00000001, 0x42A10588, "Memory");// FLEXSPI2_B_DATA00 + __writeMemory32(0x00000000, 0x42A10578, "Memory");// FLEXSPI2_A_DATA00 + __writeMemory32(0x00000000, 0x42A1057C, "Memory");// FLEXSPI2_A_DATA01 + __writeMemory32(0x00000000, 0x42A10580, "Memory");// FLEXSPI2_A_DATA02 + __writeMemory32(0x00000000, 0x42A10584, "Memory");// FLEXSPI2_A_DATA03 + __writeMemory32(0x00000000, 0x42A10570, "Memory");// FLEXSPI2_A_DQS + __writeMemory32(0x00000000, 0x42A10598, "Memory");// FLEXSPI2_A_SCLK + + // PAD ctrl + __writeMemory32(0x00000008, 0x42A102D0, "Memory");// FLEXSPI2_B_DATA03 + __writeMemory32(0x00000008, 0x42A102D4, "Memory");// FLEXSPI2_B_DATA02 + __writeMemory32(0x00000008, 0x42A102D8, "Memory");// FLEXSPI2_B_DATA01 + __writeMemory32(0x00000008, 0x42A102DC, "Memory");// FLEXSPI2_B_DATA00 + __writeMemory32(0x00000008, 0x42A102E4, "Memory");// FLEXSPI2_A_DATA00 + __writeMemory32(0x00000008, 0x42A102E8, "Memory");// FLEXSPI2_A_DATA01 + __writeMemory32(0x00000008, 0x42A102EC, "Memory");// FLEXSPI2_A_DATA02 + __writeMemory32(0x00000008, 0x42A102F0, "Memory");// FLEXSPI2_A_DATA03 + __writeMemory32(0x00000008, 0x42A102F4, "Memory");// FLEXSPI2_A_SS0_B + __writeMemory32(0x00000008, 0x42A102F8, "Memory");// FLEXSPI2_A_DQS + __writeMemory32(0x00000008, 0x42A102FC, "Memory");// FLEXSPI2_A_SCLK +} + +_FLEXSPI2_ClockInit() +{ + __writeMemory32(0x0, 0x54484350, "Memory"); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + __writeMemory32(0x101, 0x44450B00, "Memory"); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +_FLEXSPI2_ModuleInit() +{ + // Config FlexSPI2 Registers + + __var reg; + reg = __readMemory32(0x445E0000, "Memory"); + __writeMemory32((reg & 0xFFFFFFFD), 0x445E0000, "Memory"); + + _FLEXSPI2_ModuleReset(); + + __writeMemory32(0xFFFF3032, 0x445E0000, "Memory"); // MCR0 + __writeMemory32(0xFFFFFFFF, 0x445E0004, "Memory"); // MCR1 + __writeMemory32(0x200001F7, 0x445E0008, "Memory"); // MCR2 + __writeMemory32(0x00000078, 0x445E000C, "Memory"); // AHBCR prefetch enable + __writeMemory32(0x800F0000, 0x445E0020, "Memory"); // AHBRXBUF0CR0 + __writeMemory32(0x800F0000, 0x445E0024, "Memory"); // AHBRXBUF1CR0 + __writeMemory32(0x800F0000, 0x445E0028, "Memory"); // AHBRXBUF2CR0 + __writeMemory32(0x800F0000, 0x445E002C, "Memory"); // AHBRXBUF3CR0 + __writeMemory32(0x800F0000, 0x445E0030, "Memory"); // AHBRXBUF4CR0 + __writeMemory32(0x800F0000, 0x445E0034, "Memory"); // AHBRXBUF5CR0 + __writeMemory32(0x80000020, 0x445E0038, "Memory"); // AHBRXBUF6CR0 + __writeMemory32(0x80000020, 0x445E003C, "Memory"); // AHBRXBUF7CR0 + __writeMemory32(0x00000000, 0x445E00B8, "Memory"); // IPRXFCR + __writeMemory32(0x00000000, 0x445E00BC, "Memory"); // IPTXFCR + + __writeMemory32(0x00000000, 0x445E0060, "Memory"); // FLASHA1CR0 + __writeMemory32(0x00000000, 0x445E0064, "Memory"); // FLASHA2CR0 + __writeMemory32(0x00000000, 0x445E0068, "Memory"); // FLASHB1CR0 + __writeMemory32(0x00000000, 0x445E006C, "Memory"); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + __writeMemory32(0x00002000, 0x445E0060, "Memory"); // FLASHA1CR0 + __writeMemory32(0x00021C63, 0x445E0070, "Memory"); // FLASHA1CR1 + __writeMemory32(0x00000100, 0x445E0080, "Memory"); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + __writeMemory32(0x00000079, 0x445E00C0, "Memory"); // DLLCRA + __writeMemory32(0xFFFF3030, 0x445E0000, "Memory"); // MCR0 + + do + { + reg = __readMemory32(0x445E00E8, "Memory"); + } while (0x3 != (reg & 0x3)); + __delay(1000); // 1ms + + __writeMemory32(0xFFFF3032, 0x445E0000, "Memory"); // MCR0 + __writeMemory32(0x000000C2, 0x445E0094, "Memory"); // FLASHCR4 + __writeMemory32(0x000000C6, 0x445E0094, "Memory"); // FLASHCR4 + __writeMemory32(0xFFFF3030, 0x445E0000, "Memory"); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + __writeMemory32(0x5AF05AF0, 0x445E0018, "Memory"); // LUTKEY + __writeMemory32(0x00000002, 0x445E001C, "Memory"); // LUTCR + __writeMemory32(0x8B1887A0, 0x445E0200, "Memory"); // LUT[0] + __writeMemory32(0xB7078F10, 0x445E0204, "Memory"); // LUT[1] + __writeMemory32(0x0000A704, 0x445E0208, "Memory"); // LUT[2] + __writeMemory32(0x00000000, 0x445E020C, "Memory"); // LUT[3] + __writeMemory32(0x8B188720, 0x445E0210, "Memory"); // LUT[4] + __writeMemory32(0xB7078F10, 0x445E0214, "Memory"); // LUT[5] + __writeMemory32(0x0000A304, 0x445E0218, "Memory"); // LUT[6] + __writeMemory32(0x00000000, 0x445E021C, "Memory"); // LUT[7] + __writeMemory32(0x8B1887E0, 0x445E0220, "Memory"); // LUT[8] + __writeMemory32(0xB7078F10, 0x445E0224, "Memory"); // LUT[9] + __writeMemory32(0x0000A704, 0x445E0228, "Memory"); // LUT[10] + __writeMemory32(0x00000000, 0x445E022C, "Memory"); // LUT[11] + __writeMemory32(0x8B188760, 0x445E0230, "Memory"); // LUT[12] + __writeMemory32(0xA3028F10, 0x445E0234, "Memory"); // LUT[13] + __writeMemory32(0x00000000, 0x445E0238, "Memory"); // LUT[14] + __writeMemory32(0x00000000, 0x445E023C, "Memory"); // LUT[15] + __writeMemory32(0x00000000, 0x445E0240, "Memory"); // LUT[16] + __writeMemory32(0x00000000, 0x445E0244, "Memory"); // LUT[17] + __writeMemory32(0x00000000, 0x445E0248, "Memory"); // LUT[18] + __writeMemory32(0x00000000, 0x445E024C, "Memory"); // LUT[19] + __writeMemory32(0x5AF05AF0, 0x445E0018, "Memory"); // LUTKEY + __writeMemory32(0x00000001, 0x445E001C, "Memory"); // LUTCR + + /* Restore hyperram CR0 register */ + __writeMemory32(0x00001000, 0x445E00A0, "Memory"); // IPCR0 + __writeMemory32(0x00030002, 0x445E00A4, "Memory"); // IPCR1 + __writeMemory32(0x00000001, 0x445E00BC, "Memory"); // IPTXFCR + __writeMemory32(0x2F8F2F8F, 0x445E0180, "Memory"); // TFDR 0x8F2F is default value of W756/7x of CR0 + __writeMemory32(0x00000040, 0x445E0014, "Memory"); // INTR + __writeMemory32(0x00000001, 0x445E00B0, "Memory"); // IPCMD + do + { + reg = __readMemory32(0x445E0014, "Memory"); // INTR + } while ((reg & 0x1) == 0x0); + __writeMemory32(0x00000001, 0x445E0014, "Memory"); // INTR + + /* Restore hyperram CR1 register */ + __writeMemory32(0x00001002, 0x445E00A0, "Memory"); // IPCR0 + __writeMemory32(0x00030002, 0x445E00A4, "Memory"); // IPCR1 + __writeMemory32(0x00000001, 0x445E00BC, "Memory"); // IPTXFCR + __writeMemory32(0xC1FFC1FF, 0x445E0180, "Memory"); // TFDR 0xFFC1 is default value of W756/7x of CR1 + __writeMemory32(0x00000040, 0x445E0014, "Memory"); // INTR + __writeMemory32(0x00000001, 0x445E00B0, "Memory"); // IPCMD + do + { + reg = __readMemory32(0x445E0014, "Memory"); // INTR + } while ((reg & 0x1) == 0x0); + __writeMemory32(0x00000001, 0x445E0014, "Memory"); // INTR + + _FLEXSPI2_ModuleReset(); +} + +HyperRAM_Init() +{ + __message "Init HyperRAM"; + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + __message "HyperRAM init done\n"; +} + +Flash_Init() +{ + __message "Init Flash"; + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + __message "Flash init done\n"; +} + +execUserPreload() +{ + Flash_Init(); + HyperRAM_Init(); +} + +execUserReset() +{ + Flash_Init(); + HyperRAM_Init(); +} + +CleanInvalidateCache(cache) +{ + __var reg; + reg = __readMemory32(cache, "Memory"); + if((reg & 0x01) != 0) + { + __writeMemory32(0x0F000000 | reg, cache, "Memory"); + __writeMemory32(0x8F000000 | reg, cache, "Memory"); + + do + { + reg = __readMemory32(cache, "Memory"); + } while (( reg & 0x80000000) != 0); + } +} + +execUserExecutionStarted() +{ + /* + CMSIS-DAP probably use software breakpoint by default, + which fails debug for those code within cached memory, + e.g. hyperram_txt_debug/release. + With cache operation below, it helps debug for software + breakpoint, but still fails in assembly instruction + step debug, since execUserExecutionStarted is not invoked + in assembly instruction setp debug. + + The final solution for cached memory code debug, is to use + hardware breakpoint, which can be set in IAR project option: + Debug->CMSIS DAP->breakpoint. + */ + + __var reg; + reg = __readMemory32(0xE000ED00, "Memory"); // SCB->CPUID + if(__driverType("cmsisdap") && (reg == 0x411FD210)) + { + // CMSIS-DAP and CM33 core + CleanInvalidateCache(0x44400000); // XCACHE_PC_CCR + CleanInvalidateCache(0x44400800); // XCACHE_PS_CCR + } +} \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_cm7.jlinkscript b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_cm7.jlinkscript new file mode 100644 index 00000000000..24be3e988fc --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/evkmimxrt1180_cm7.jlinkscript @@ -0,0 +1,1041 @@ +__constant U32 _INDEX_AHB_AP_CORTEX_M33 = 3; +__constant U32 _AHB_ACC_32BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (2 << 0); +__constant U32 _AHB_ACC_16BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (1 << 0); // HMASTER = DEBUG, Private access, no Auto-increment, Access size: half word; +__constant U32 _ACCESS_AP = 1; +__constant U32 _CM33_CPUID = 0xD210; +__constant U32 _CM7_CPUID = 0x0C27; + +/* ROM trap address for CM33 core, after system reset */ +__constant U32 _ROM_TRAP0_ADDR = 0x10002932; +__constant U32 _ROM_TRAP1_ADDR = 0x100025D4; +__constant U32 _ROM_TRAP2_ADDR = 0x100025D4; + +__constant U32 _SRC_SRSR_ADDR = 0x44460050; +__constant U32 _SRC_SRMASK_ADDR = 0x44460018; +__constant U32 _SRC_SCR_ADDR = 0x44460010; +__constant U32 _SRC_AUTHEN_CTRL_ADDR = 0x44460004; +__constant U32 _SRC_SBMR2_ADDR = 0x44460044; +__constant U32 _BLK_M7_CFG_ADDR = 0x444F0080; + +__constant U32 _DWT_COMP0_ADDR = 0xE0001020; +__constant U32 _DWT_FUNC0_ADDR = 0xE0001028; + +__constant U32 _DCB_DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DCB_DEMCR_ADDR = 0xE000EDFC; + +__constant U32 _SCB_AIRCR_ADDR = 0xE000ED0C; + +__constant U32 _XCACHE_PC_CCR_ADDR = 0x44400000; +__constant U32 _XCACHE_PS_CCR_ADDR = 0x44400800; + +__constant U32 _CM33_MPU_CTRL_ADDR = 0xE000ED94; + +__constant U32 _SI_VER_ADDR = 0x5751804C; + +unsigned int cpuID; +unsigned int rom_trap_addr; + +static int _WriteViaCM33AP16(U32 Addr, U16 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + Data = (Data & 0xFFFF) | ((Data & 0xFFFF) << 16); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP16(U32 Addr) { + U32 r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +static int _WriteViaCM33AP32(U32 Addr, U32 Data) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP32(U32 Addr) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +/* For Debug Start */ +__constant U32 _DCB_DCRSR_ADDR = 0xE000EDF4; +__constant U32 _DCB_DCRDR_ADDR = 0xE000EDF8; +__constant U32 _SCB_DFSR_ADDR = 0xE000ED30; + +__constant U32 _REG_R0 = 0x0; +__constant U32 _REG_R1 = 0x1; +__constant U32 _REG_R2 = 0x2; +__constant U32 _REG_R3 = 0x3; +__constant U32 _REG_R4 = 0x4; +__constant U32 _REG_R5 = 0x5; +__constant U32 _REG_R6 = 0x6; +__constant U32 _REG_R7 = 0x7; +__constant U32 _REG_R8 = 0x8; +__constant U32 _REG_R9 = 0x9; +__constant U32 _REG_R10 = 0xA; +__constant U32 _REG_R11 = 0xB; +__constant U32 _REG_R12 = 0xC; +__constant U32 _REG_SP = 0xD; +__constant U32 _REG_LR = 0xE; +__constant U32 _REG_PC = 0xF; +__constant U32 _REG_SP_main = 0x11; +__constant U32 _REG_SP_process = 0x12; +__constant U32 _REG_MSPLIM_S = 0x1C; +__constant U32 _REG_PSPLIM_S = 0x1D; +__constant U32 _REG_MSPLIM_NS = 0x1E; +__constant U32 _REG_PSPLIM_NS = 0x1F; + +static U32 _ReadCPUReg(int RegIndex) { + U32 v; + + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRSR_ADDR); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, RegIndex); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRDR_ADDR); + v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA); + return v; +} + +static U32 _ReadCPURegViaAP(int AP, int RegIndex) { + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (AP << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + + r = _ReadCPUReg(RegIndex); + return r; +} + +int debug = 0; + +void ShowDAPInfo(void) +{ + int r; + + if ( debug ) + { + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + r = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_CTRL); + JLINK_SYS_Report1("CM33 AP CSW = ", r); + } +} + +void DBG_ShowCM33Reg(void) +{ + int r, sp, pc; + + r = _ReadViaCM33AP32(_CM33_MPU_CTRL_ADDR); + JLINK_SYS_Report1(" CM33 MPU_CTRL = ", r); + r = _ReadViaCM33AP32(_XCACHE_PC_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PC_CCR = ", r); + r = _ReadViaCM33AP32(_XCACHE_PS_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PS_CCR = ", r); + + r = _ReadViaCM33AP32(_DWT_COMP0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_COMP0 = ", r); + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_FUNC0 = ", r); + + r = _ReadViaCM33AP32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" CM33 DFSR = ", r); + r = _ReadViaCM33AP32(_DCB_DEMCR_ADDR); + JLINK_SYS_Report1(" CM33 DEMCR = ", r); + r = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" CM33 DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_SP); + pc = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_PC); + JLINK_SYS_Report1(" CM33 PC = ", pc); + JLINK_SYS_Report1(" CM33 SP = ", sp); + } + else + { + JLINK_SYS_Report(" CM33 core is not halted!"); + } +} + +void DBG_ShowCoreReg(void) +{ + int r, sp, pc; + + r = JLINK_MEM_ReadU32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" DFSR = ", r); + r = JLINK_MEM_ReadU32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" DHCSR = ", r); + if ( (r & 0x02) != 0) + { + sp = _ReadCPUReg(_REG_SP); + pc = _ReadCPUReg(_REG_PC); + JLINK_SYS_Report1(" PC = ", pc); + JLINK_SYS_Report1(" SP = ", sp); + } + else + { + JLINK_SYS_Report(" Core is not halted!"); + } +} + +void DBG_ShowReg(int seq) +{ + int r; + if( debug ) + { + JLINK_SYS_Report1("Seq: ", seq); + + r = _ReadViaCM33AP32(_SRC_AUTHEN_CTRL_ADDR); + JLINK_SYS_Report1(" AUTHEN_CTRL = ", r); + r = _ReadViaCM33AP32(_SRC_SRSR_ADDR); + JLINK_SYS_Report1(" SRSR = ", r); + r = _ReadViaCM33AP32(_SRC_SRMASK_ADDR); + JLINK_SYS_Report1(" SRMASK = ", r); + r = _ReadViaCM33AP32(_SRC_SCR_ADDR); + JLINK_SYS_Report1(" SCR = ", r); + r = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + JLINK_SYS_Report1(" M7_CFG = ", r); + + if(cpuID == _CM7_CPUID) + { + if((r & 0x10) == 0) + { + DBG_ShowCoreReg(); + } + + } + + DBG_ShowCM33Reg(); + } +} +/* For Debug End */ + +void _FLEXSPI1_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI1_WaitBusIdle() +{ + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FLEXSPI1_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + MEM_WriteU32(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +void _FLEXSPI1_SetPinForQuadMode(void) { + // Set 4 Pin Mode for JLink + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + MEM_WriteU32(0x42A1023C, 0x17); + MEM_WriteU32(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + MEM_WriteU32(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + MEM_WriteU32(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + MEM_WriteU32(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + MEM_WriteU32(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + MEM_WriteU32(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + MEM_WriteU32(0x42A10254, 0x17); +} + +void _FLEXSPI1_ModuleInit(void) { + + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg & 0xFFFFFFFD)); + + //FLEXSPI1->MCR0 = 0xFFFF8010; + MEM_WriteU32(0x425E0000, 0xFFFF8010); + //FLEXSPI1->MCR2 = 0x200001F7; + MEM_WriteU32(0x425E0008, 0x200001F7); + //FLEXSPI1->AHBCR = 0x78; + MEM_WriteU32(0x425E000C, 0x78); + + //FLEXSPI1->FLSHCR0[0] = 0x00004000; + MEM_WriteU32(0x425E0060, 0x00004000); + + + //FLEXSPI1->FLSHCR4 = 0xC3; + MEM_WriteU32(0x425E0094, 0xC3); + //FLEXSPI1->IPRXFCR = 0x1C; + MEM_WriteU32(0x425E00B8, 0x1C); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x02; + MEM_WriteU32(0x425E001C, 0x02); + + //FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + MEM_WriteU32(0x425E0200, 0x0A1804EB); + //FLEXSPI1->LUT[1] = 0x26043206; + MEM_WriteU32(0x425E0204, 0x26043206); + //FLEXSPI1->LUT[2] = 0x00000000; + MEM_WriteU32(0x425E0208, 0x00000000); + //FLEXSPI1->LUT[3] = 0x00000000; + MEM_WriteU32(0x425E020C, 0x00000000); + + //FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + MEM_WriteU32(0x425E0210, 0x00000406); + //FLEXSPI1->LUT[5] = 0x00000000; + MEM_WriteU32(0x425E0214, 0x00000000); + //FLEXSPI1->LUT[6] = 0x00000000; + MEM_WriteU32(0x425E0218, 0x00000000); + //FLEXSPI1->LUT[7] = 0x00000000; + MEM_WriteU32(0x425E021C, 0x00000000); + + //FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + MEM_WriteU32(0x425E0220, 0x20040401); + //FLEXSPI1->LUT[9] = 0x00000000; + MEM_WriteU32(0x425E0224, 0x00000000); + //FLEXSPI1->LUT[10] = 0x00000000; + MEM_WriteU32(0x425E0228, 0x00000000); + //FLEXSPI1->LUT[11] = 0x00000000; + MEM_WriteU32(0x425E022C, 0x00000000); + + //FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + MEM_WriteU32(0x425E0230, 0x24040405); + //FLEXSPI1->LUT[13] = 0x00000000; + MEM_WriteU32(0x425E0234, 0x00000000); + //FLEXSPI1->LUT[14] = 0x00000000; + MEM_WriteU32(0x425E0238, 0x00000000); + //FLEXSPI1->LUT[15] = 0x00000000; + MEM_WriteU32(0x425E023C, 0x00000000); + + //FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + MEM_WriteU32(0x425E0240, 0x00000404); + //FLEXSPI1->LUT[17] = 0x00000000; + MEM_WriteU32(0x425E0244, 0x00000000); + //FLEXSPI1->LUT[18] = 0x00000000; + MEM_WriteU32(0x425E0248, 0x00000000); + //FLEXSPI1->LUT[19] = 0x00000000; + MEM_WriteU32(0x425E024C, 0x00000000); + + //FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + MEM_WriteU32(0x425E0250, 0x20040431); + //FLEXSPI1->LUT[21] = 0x00000000; + MEM_WriteU32(0x425E0254, 0x00000000); + //FLEXSPI1->LUT[22] = 0x00000000; + MEM_WriteU32(0x425E0258, 0x00000000); + //FLEXSPI1->LUT[23] = 0x00000000; + MEM_WriteU32(0x425E025C, 0x00000000); + + //FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + MEM_WriteU32(0x425E0260, 0x24040435); + //FLEXSPI1->LUT[25] = 0x00000000; + MEM_WriteU32(0x425E0264, 0x00000000); + //FLEXSPI1->LUT[26] = 0x00000000; + MEM_WriteU32(0x425E0268, 0x00000000); + //FLEXSPI1->LUT[27] = 0x00000000; + MEM_WriteU32(0x425E026C, 0x00000000); + + //FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + MEM_WriteU32(0x425E0270, 0x00000450); + //FLEXSPI1->LUT[29] = 0x00000000; + MEM_WriteU32(0x425E0274, 0x00000000); + //FLEXSPI1->LUT[30] = 0x00000000; + MEM_WriteU32(0x425E0278, 0x00000000); + //FLEXSPI1->LUT[31] = 0x00000000; + MEM_WriteU32(0x425E027C, 0x00000000); + + //FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + //FLEXSPI1->LUTCR = 0x01; + MEM_WriteU32(0x425E001C, 0x01); +} + +void _FLEXSPI2_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg | 0x1)); + do + { + reg = MEM_ReadU32(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI2_WaitBusIdle() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if( (reg & 0x02) == 0) // Module Enabled + { + do + { + reg = MEM_ReadU32(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FlexSPI2_SetPinForOctalMode() +{ + // Config IOMUX for FlexSPI2 + MEM_WriteU32(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + //The input daisy!! + MEM_WriteU32(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + MEM_WriteU32(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +void _FLEXSPI2_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + MEM_WriteU32(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +void _FLEXSPI2_ModuleInit() +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0004, 0xFFFFFFFF); // MCR1 + MEM_WriteU32(0x445E0008, 0x200001F7); // MCR2 + MEM_WriteU32(0x445E000C, 0x00000078); // AHBCR prefetch enable + MEM_WriteU32(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + MEM_WriteU32(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + MEM_WriteU32(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + MEM_WriteU32(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + MEM_WriteU32(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + MEM_WriteU32(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + MEM_WriteU32(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + MEM_WriteU32(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + MEM_WriteU32(0x445E00B8, 0x00000000); // IPRXFCR + MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR + + MEM_WriteU32(0x445E0060, 0x00000000); // FLASHA1CR0 + MEM_WriteU32(0x445E0064, 0x00000000); // FLASHA2CR0 + MEM_WriteU32(0x445E0068, 0x00000000); // FLASHB1CR0 + MEM_WriteU32(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0060, 0x00002000); // FLASHA1CR0 + MEM_WriteU32(0x445E0070, 0x00021C63); // FLASHA1CR1 + MEM_WriteU32(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E00C0, 0x00000079); // DLLCRA + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + do + { + reg = MEM_ReadU32(0x445E00E8); + } while (0x3 != (reg & 0x3)); + JLINK_SYS_Sleep(1); + // __delay(100);//100us + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0094, 0x000000C2); // FLASHCR4 + MEM_WriteU32(0x445E0094, 0x000000C6); // FLASHCR4 + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000002); // LUTCR + MEM_WriteU32(0x445E0200, 0x8B1887A0); // LUT[0] + MEM_WriteU32(0x445E0204, 0xB7078F10); // LUT[1] + MEM_WriteU32(0x445E0208, 0x0000A704); // LUT[2] + MEM_WriteU32(0x445E020C, 0x00000000); // LUT[3] + MEM_WriteU32(0x445E0210, 0x8B188720); // LUT[4] + MEM_WriteU32(0x445E0214, 0xB7078F10); // LUT[5] + MEM_WriteU32(0x445E0218, 0x0000A304); // LUT[6] + MEM_WriteU32(0x445E021C, 0x00000000); // LUT[7] + MEM_WriteU32(0x445E0220, 0x8B1887E0); // LUT[8] + MEM_WriteU32(0x445E0224, 0xB7078F10); // LUT[9] + MEM_WriteU32(0x445E0228, 0x0000A704); // LUT[10] + MEM_WriteU32(0x445E022C, 0x00000000); // LUT[11] + MEM_WriteU32(0x445E0230, 0x8B188760); // LUT[12] + MEM_WriteU32(0x445E0234, 0xA3028F10); // LUT[13] + MEM_WriteU32(0x445E0238, 0x00000000); // LUT[14] + MEM_WriteU32(0x445E023C, 0x00000000); // LUT[15] + MEM_WriteU32(0x445E0240, 0x00000000); // LUT[16] + MEM_WriteU32(0x445E0244, 0x00000000); // LUT[17] + MEM_WriteU32(0x445E0248, 0x00000000); // LUT[18] + MEM_WriteU32(0x445E024C, 0x00000000); // LUT[19] + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + MEM_WriteU32(0x445E00A0, 0x00001000); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + MEM_WriteU32(0x445E00A0, 0x00001002); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do + { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +void CM7_InitTCM(U32 targetAddr, U32 size) { + U32 reg; + + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + + if((reg & 0x80000000) != 0) + { + // DMA channel is active, wait it get finished + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + } + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag + + _WriteViaCM33AP32(0x5201002C, 0x00000000); // DMA4->TCD[0].SLAST_SGA + _WriteViaCM33AP32(0x52010038, 0x00000000); // DMA4->TCD[0].DLAST_SGA + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR + + _WriteViaCM33AP32(0x52010020, 0x20484000); // DMA4->TCD[0].SADDR + _WriteViaCM33AP32(0x52010030, targetAddr); // DMA4->TCD[0].DADDR + _WriteViaCM33AP32(0x52010028, size); // DMA4->TCD[0].NBYTES_MLOFFNO + _WriteViaCM33AP16(0x52010036, 0x1); // DMA4->TCD[0].ELINKNO + _WriteViaCM33AP16(0x5201003E, 0x1); // DMA4->TCD[0].BITER_ELINKNO + _WriteViaCM33AP16(0x52010026, 0x0303); // DMA4->TCD[0].ATTR + _WriteViaCM33AP16(0x52010024, 0x0); // DMA4->TCD[0].SOFF + _WriteViaCM33AP16(0x52010034, 0x8); // DMA4->TCD[0].DOFF + _WriteViaCM33AP32(0x52010000, 0x7); // DMA4->TDC[0].CH_CSR + _WriteViaCM33AP16(0x5201003C, 0x8); // DMA4->TCD[0].CSR + _WriteViaCM33AP16(0x5201003C, 0x9); // DMA4->TCD[0].CSR + + do + { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while((reg & 0x40000000) == 0); + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag +} + +void CM7_KickOff(int ecc_init) +{ + U32 reg, resp1, resp2; + + reg = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + if((reg & 0x10) == 0) + { + JLINK_SYS_Report("CM7 is running already"); + } + else + { + JLINK_SYS_Report("************* Begin Operations to Enable CM7 ***********************"); + + // Clock Preparation + JLINK_SYS_Report("******** Prepare Clock *********"); + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + _WriteViaCM33AP32(0x54450000, 0x100); // CLOCK_ROOT[0].CONTROL, CM7 + + // Release CM7 + _WriteViaCM33AP32(_SRC_SCR_ADDR, 0x1); + + if (ecc_init) + { + // DMA initialization + JLINK_SYS_Report("******** DMA operation *********"); + CM7_InitTCM(0x303C0000, 0x40000); + CM7_InitTCM(0x30400000, 0x40000); + } + + // Making Landing Zone + JLINK_SYS_Report("******** Creating Landing Zone *********"); + _WriteViaCM33AP32(0x303C0000, 0x20020000); + _WriteViaCM33AP32(0x303C0004, 0x00000009); + _WriteViaCM33AP32(0x303C0008, 0xE7FEE7FE); + + // VTOR 0x00 + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0010); + + // Trigger ELE + JLINK_SYS_Report("******** ELE Trigger *********"); + _WriteViaCM33AP32(0x57540200, 0x17d20106); // MU_RT_S3MUA->TR[0] + resp1 = _ReadViaCM33AP32(0x57540280); // MU_RT_S3MUA->RR[0] + resp2 = _ReadViaCM33AP32(0x57540284); // MU_RT_S3MUA->RR[1] + JLINK_SYS_Report1("ELE RESP1 : ", resp1); + JLINK_SYS_Report1("ELE RESP2 : ", resp2); + + // Deassert CM7 Wait + JLINK_SYS_Report("******** Kickoff CM7 *********"); + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0); + } +} + +void DAP_Init(void) +{ + JLINK_CORESIGHT_Configure(""); + + CORESIGHT_AddAP(0, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(1, CORESIGHT_APB_AP); + CORESIGHT_AddAP(2, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(3, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(4, CORESIGHT_APB_AP); + CORESIGHT_AddAP(5, CORESIGHT_APB_AP); + CORESIGHT_AddAP(6, CORESIGHT_APB_AP); + + JLINK_SYS_Report("***************************************************"); + if(cpuID == _CM7_CPUID) + { + CPU = CORTEX_M7; + CORESIGHT_IndexAHBAPToUse = 2; + JLINK_SYS_Report("Current core is CM7"); + } + else if(cpuID == _CM33_CPUID) + { + CPU = CORTEX_M33; + CORESIGHT_IndexAHBAPToUse = 3; + JLINK_SYS_Report("Current core is CM33"); + + ShowDAPInfo(); + CORESIGHT_AHBAPCSWDefaultSettings = (1<<29)|(1<<25)|(1<<24); + } + else + { + JLINK_SYS_Report1("Wrong CPU ID: ", cpuID); + } + JLINK_SYS_Report("***************************************************"); +} + +void CM33_Halt(void) +{ + U32 reg; + + reg = (_ReadViaCM33AP32(_SRC_SBMR2_ADDR) >> 24) & 0x3F; + + if((reg == 8) || (reg == 9)) // Serial Download Mode, or Boot From Fuse + { + JLINK_SYS_Report("Not flash execution mode, check if CM33 is halted..."); + + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + + if(0 == (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is not halted, trying to halt it. CM33 DHCSR: ", reg); + + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0001); // Enable CM33 debug control + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Halt CM33 + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + if(0 != (reg & 0x02)) + { + JLINK_SYS_Report1("CM33 is halted now. CM33 DHCSR: ", reg); + } + else + { + JLINK_SYS_Report1("CM33 still running, halt failed. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report1("CM33 is halted. CM33 DHCSR: ", reg); + } + } + else + { + JLINK_SYS_Report("Flash execution mode, leave CM33 run status as it was..."); + } +} + +void Flash_Init() { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init Flash"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void HyperRAM_Init() +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init HyperRAM"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void CM33_ClearNVIC(void) { + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Clear NVIC"); + JLINK_SYS_Report("***************************************************"); + JLINK_MEM_Fill(0xE000E180, 0x40, 0xFF); + JLINK_MEM_Fill(0xE000E280, 0x40, 0xFF); +} + +int InitTarget(void) +{ + int r; + cpuID = _CM7_CPUID; + + DAP_Init(); + + if(cpuID == _CM7_CPUID) + { + CM33_Halt(); + CM7_KickOff(1); + + /* Avoid to access TPIU to prevent soc hang */ + JLINK_ExecCommand("map region 0xE0040000-0xE0040FFF X"); // Mark region as illegal + } + + r = _ReadViaCM33AP32(_SI_VER_ADDR) & 0xF; + + if ( r == 1 ) + { + rom_trap_addr = _ROM_TRAP1_ADDR; + } + else if ( r == 2 ) + { + rom_trap_addr = _ROM_TRAP2_ADDR; + } + else + { + rom_trap_addr = _ROM_TRAP0_ADDR; + } + JLINK_SYS_Report1("SI_VER = ", r); + JLINK_SYS_Report1("TRAP = ", rom_trap_addr); + + return 0; +} + +int SetupTarget(void) +{ + return 0; +} + +void ResetTarget_CM33(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + + core_reset_request_bit_mask = 0x100; /* for CM33 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM33 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM33 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + ShowDAPInfo(); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + JLINK_SYS_Report("Set CM33 watch point"); + comp = JLINK_MEM_ReadU32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later */ + func = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, rom_trap_addr); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, 0x00000412); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped!"); + } + + DBG_ShowReg(4); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM33 watch point"); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, comp); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM33 is not halted after reset!"); + } +} + +void ResetTarget_CM7(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + int mem_0, mem_1, mem_2; + + core_reset_request_bit_mask = 0x400; /* for CM7 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) + { + JLINK_SYS_Report("ERR: CM7 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ( (r & core_reset_request_bit_mask) != 0 ) + { + if ( (r & (core_reset_request_bit_mask<<16)) == 0 ) + { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ( (r & 0x80) == 0 ) + { + JLINK_SYS_Report("Enable system reset via CM7 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask are locked!"); + } + } + else + { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + /* CM7_KickOff will use the first 3 words(32bits) of CM7 ITCM, save and restore them later */ + mem_0 = JLINK_MEM_ReadU32(0); + mem_1 = JLINK_MEM_ReadU32(4); + mem_2 = JLINK_MEM_ReadU32(8); + + JLINK_SYS_Report("Set CM33 watch point"); + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Enable Debug and halt CM33 core + comp = _ReadViaCM33AP32(_DWT_COMP0_ADDR); /* Save the DWT register and restore them later after reset */ + func = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + _WriteViaCM33AP32(_DCB_DEMCR_ADDR, 0x01000000); // Enable DWT of CM33 core + _WriteViaCM33AP32(_DWT_COMP0_ADDR, rom_trap_addr); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, 0x00000412); + + DBG_ShowReg(4); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) + { + JLINK_SYS_Report("ERR: CM33 core is not trapped after reset!"); + } + + DBG_ShowReg(5); + + CM7_KickOff(0); + + // Halt CM7 core + JLINK_MEM_WriteU32(_DCB_DHCSR_ADDR, 0xA05F0003); + + DBG_ShowReg(6); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) + { + JLINK_SYS_Report("restore CM7 ITCM"); + + JLINK_MEM_WriteU32(0, mem_0); + JLINK_MEM_WriteU32(4, mem_1); + JLINK_MEM_WriteU32(8, mem_2); + + JLINK_SYS_Report("restore CM33 watch points"); + _WriteViaCM33AP32(_DWT_COMP0_ADDR, comp); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, func); + } + else + { + JLINK_SYS_Report("ERR: CM7 core can not be halted!"); + } +} + +void ResetTarget(void) { + if(cpuID == _CM7_CPUID) + { + ResetTarget_CM7(); + } + else if(cpuID == _CM33_CPUID) + { + ResetTarget_CM33(); + } +} + +int AfterResetTarget(void) +{ + U32 reg; + + if(cpuID == _CM33_CPUID) + { + // CM33 NVIC may be enabled by ROM after reset + CM33_ClearNVIC(); + } + + Flash_Init(); + HyperRAM_Init(); + + return 0; +} diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/figures/board.png b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/figures/board.png new file mode 100644 index 00000000000..19bde56131a Binary files /dev/null and b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/figures/board.png differ diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h new file mode 100644 index 00000000000..15c92e3a07c --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.h @@ -0,0 +1,437 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 4096 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define ARCH_USING_HW_ATOMIC_8 +#define ARCH_USING_HW_ATOMIC_16 +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_M33 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 4096 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +#define PKG_USING_CMBACKTRACE +#define PKG_CMBACKTRACE_PLATFORM_M33 +#define PKG_CMBACKTRACE_DUMP_STACK +#define PKG_CMBACKTRACE_PRINT_ENGLISH +#define PKG_USING_CMBACKTRACE_V10401 +#define PKG_CMBACKTRACE_VER_NUM 0x10401 +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +#define PKG_USING_NXP_IMXRT_DRIVER +#define PKG_USING_NXP_IMXRT_DRIVER_LATEST_VERSION +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +/* end of HPMicro SDK */ + +/* FT32 HAL & SDK Drivers */ + +/* end of FT32 HAL & SDK Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_IMXRT1180_SERIES + +/* Hardware Drivers Config */ + +#define BSP_USING_QSPIFLASH +#define SOC_MIMXRT1189CVM8C +#define SOC_MIMXRT1189CVM8C_CM7 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_LPUART +#define BSP_USING_LPUART1 +/* end of On-chip Peripheral Drivers */ + +/* Onboard Peripheral Drivers */ + +/* end of Onboard Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py new file mode 100644 index 00000000000..6261a74efc8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/rtconfig.py @@ -0,0 +1,205 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files/IAR Systems/Embedded Workbench 9.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +#BUILD = 'debug' +BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link_ram.lds' + + CPATH = '' + LPATH = '' + + AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA' + AFLAGS += ' -D__STARTUP_CLEAR_BSS' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board/linker_scripts/link_ram.scf"' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + CFLAGS += ' --diag_suppress=66,1296,186,6314' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + CFLAGS = ' --target=arm-arm-none-eabi' + CFLAGS += ' -mcpu=' + CPU + CFLAGS += ' -mfpu=fpv4-sp-d16' + CFLAGS += ' -mfloat-abi=hard' + CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + AFLAGS += ' -x assembler-with-cpp' + AFLAGS += ' -Wa,-mimplicit-it=thumb' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board/linker_scripts/link_ram" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu None' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link_ram.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + # sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd new file mode 100644 index 00000000000..f728737cac8 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewd @@ -0,0 +1,1620 @@ + + + 4 + + rtthread + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp new file mode 100644 index 00000000000..d283c339789 --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewp @@ -0,0 +1,1103 @@ + + + 4 + + rtthread + + ARM + + 1 + + General + 3 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 39 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 4 + + + + inputOutputBased + + + + ILINK + 0 + + 28 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewt b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewt new file mode 100644 index 00000000000..0a51a951d6d --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.ewt @@ -0,0 +1,1468 @@ + + + 4 + + rtthread + + ARM + + 1 + + C-STAT + 519 + + 519 + + 0 + + 1 + 600 + 0 + 2 + 0 + 1 + 100 + rtthread/C-STAT + + + 2.7.5 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvoptx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvoptx new file mode 100644 index 00000000000..58bc2c9beff --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\board\linker_scripts\evkmimxrt1180_ram_cm7.ini + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U603001820 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD30500000 -FC8000 -FN1 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLMIMXRT1180 CM7 FLEXSPI -FS028000000 -FL01000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN2 -FC20000 -FD20000000 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FL01000000 -FL11000000 -FS028000000 -FS128000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + diff --git a/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx new file mode 100644 index 00000000000..5e369a5e63e --- /dev/null +++ b/bsp/nxp/imx/imxrt/imxrt1180-nxp-evk/cm7/template.uvprojx @@ -0,0 +1,402 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 6150000::V6.15::ARMCLANG + 1 + + + MIMXRT1189CVM8C:cm7 + NXP + NXP.MIMXRT1189_DFP.25.06.00 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20484000,0x07c000) IRAM2(0x20500000,0x040000) IROM(0x00000000,0x028000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC20000 -FN2 -FF0MIMXRT1180_EVK_FSPI1_QSPI_CM33 -FS028000000 -FL01000000 -FF1MIMXRT1180_EVK_FSPI1_QSPI_CM7 -FS128000000 -FL11000000 -FP0($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM33.FLM) -FP1($$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\arm\MIMXRT1180_EVK_FSPI1_QSPI_CM7.FLM)) + 0 + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1189CVM8C$devices\MIMXRT1189\MIMXRT1189_cm7.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 1 + 0x0 + 0x28000 + + + 1 + 0x1ffe0000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x28000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20484000 + 0x7c000 + + + 0 + 0x20500000 + 0x40000 + + + + + + 1 + 5 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + -xc -std=gnu99 -mimplicit-float + RELOC_VECTOR + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\board\linker_scripts\link_ram.scf + + + --legacyalign + + 6439,6314 + + + + + + + + + + + + + + + + <Project Info> + 0 + 1 + + + + + diff --git a/bsp/nxp/imx/imxrt/libraries/Kconfig b/bsp/nxp/imx/imxrt/libraries/Kconfig index 0a804fb7c3c..92ba176f195 100644 --- a/bsp/nxp/imx/imxrt/libraries/Kconfig +++ b/bsp/nxp/imx/imxrt/libraries/Kconfig @@ -33,3 +33,9 @@ config SOC_IMXRT1170_SERIES select ARCH_ARM_CORTEX_M7 select ARCH_ARM_CORTEX_FPU select PKG_USING_NXP_IMXRT_DRIVER + +config SOC_IMXRT1180_SERIES + bool + select ARCH_ARM_CORTEX_M33 + select ARCH_ARM_CORTEX_FPU + select PKG_USING_NXP_IMXRT_DRIVER \ No newline at end of file diff --git a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c index 3160e870b4d..2ad546fb45e 100644 --- a/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c +++ b/bsp/nxp/imx/imxrt/libraries/drivers/drv_uart.c @@ -7,8 +7,8 @@ * Date Author Notes * 2017-10-10 Tanek the first version * 2019-5-10 misonyo add DMA TX and RX function + * 2026-4-29 Ran add RT1180 support */ - #include #ifdef BSP_USING_LPUART @@ -18,7 +18,9 @@ #include "board.h" #include "fsl_lpuart.h" #include "fsl_lpuart_edma.h" +#ifndef SOC_IMXRT1180_SERIES #include "fsl_dmamux.h" +#endif #define LOG_TAG "drv.usart" #include @@ -497,22 +499,27 @@ void edma_tx_callback(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE); } } - -static void imxrt_dma_rx_config(struct imxrt_uart *uart) -{ - RT_ASSERT(uart != RT_NULL); - - edma_transfer_config_t xferConfig; - struct rt_serial_rx_fifo *rx_fifo; - - DMAMUX_SetSource(DMAMUX, uart->dma_rx->channel, uart->dma_rx->request); - DMAMUX_EnableChannel(DMAMUX, uart->dma_rx->channel); - EDMA_CreateHandle(&uart->dma_rx->edma, DMA0, uart->dma_rx->channel); - EDMA_SetCallback(&uart->dma_rx->edma, edma_rx_callback, uart); - - rx_fifo = (struct rt_serial_rx_fifo *)uart->serial.serial_rx; - - EDMA_PrepareTransfer(&xferConfig, + static void imxrt_dma_rx_config(struct imxrt_uart *uart) + { + RT_ASSERT(uart != RT_NULL); + + edma_transfer_config_t xferConfig; + struct rt_serial_rx_fifo *rx_fifo; + + #ifndef SOC_IMXRT1180_SERIES + DMAMUX_SetSource(DMAMUX, uart->dma_rx->channel, uart->dma_rx->request); + DMAMUX_EnableChannel(DMAMUX, uart->dma_rx->channel); + #else + /* RT1180 uses EDMA4, configure DMA request source differently */ + EDMA_SetChannelMux(DMA0, uart->dma_rx->channel, uart->dma_rx->request); + #endif + + EDMA_CreateHandle(&uart->dma_rx->edma, DMA0, uart->dma_rx->channel); + EDMA_SetCallback(&uart->dma_rx->edma, edma_rx_callback, uart); + + rx_fifo = (struct rt_serial_rx_fifo *)uart->serial.serial_rx; + + EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(uart->uart_base), sizeof(uint8_t), rx_fifo->buffer, @@ -521,74 +528,123 @@ static void imxrt_dma_rx_config(struct imxrt_uart *uart) uart->serial.config.bufsz, kEDMA_PeripheralToMemory); - EDMA_SubmitTransfer(&uart->dma_rx->edma, &xferConfig); - EDMA_EnableChannelInterrupts(DMA0, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable); - EDMA_EnableAutoStopRequest(DMA0, uart->dma_rx->channel, false); - /* complement to adjust final destination address */ - uart->dma_rx->edma.base->TCD[uart->dma_rx->channel].DLAST_SGA = -(uart->serial.config.bufsz); - EDMA_StartTransfer(&uart->dma_rx->edma); - LPUART_EnableRxDMA(uart->uart_base, true); - - LPUART_EnableInterrupts(uart->uart_base, kLPUART_IdleLineInterruptEnable); - NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); - EnableIRQ(uart->irqn); - - LOG_D("%s dma rx config done\n", uart->name); -} - -static void imxrt_dma_tx_config(struct imxrt_uart *uart) -{ - RT_ASSERT(uart != RT_NULL); - - DMAMUX_SetSource(DMAMUX, uart->dma_tx->channel, uart->dma_tx->request); - DMAMUX_EnableChannel(DMAMUX, uart->dma_tx->channel); - EDMA_CreateHandle(&uart->dma_tx->edma, DMA0, uart->dma_tx->channel); - - LPUART_TransferCreateHandleEDMA(uart->uart_base, - &uart->dma_tx->uart_edma, - edma_tx_callback, - uart, - &uart->dma_tx->edma, - RT_NULL); - - LOG_D("%s dma tx config done\n", uart->name); -} - -#endif - -uint32_t GetUartSrcFreq(LPUART_Type *uart_base) -{ - uint32_t freq; -#ifdef SOC_IMXRT1170_SERIES - uint32_t base = (uint32_t) uart_base; - switch (base) - { - case LPUART1_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1); - break; - case LPUART12_BASE: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart12); - break; - default: - freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart2); - break; - } -#else - /* To make it simple, we assume default PLL and divider settings, and the only variable + EDMA_SubmitTransfer(&uart->dma_rx->edma, &xferConfig); + EDMA_EnableChannelInterrupts(DMA0, uart->dma_rx->channel, kEDMA_MajorInterruptEnable | kEDMA_HalfInterruptEnable); + EDMA_EnableAutoStopRequest(DMA0, uart->dma_rx->channel, false); + /* complement to adjust final destination address */ + uart->dma_rx->edma.base->TCD[uart->dma_rx->channel].DLAST_SGA = -(uart->serial.config.bufsz); + EDMA_StartTransfer(&uart->dma_rx->edma); + LPUART_EnableRxDMA(uart->uart_base, true); + + LPUART_EnableInterrupts(uart->uart_base, kLPUART_IdleLineInterruptEnable); + NVIC_SetPriority(uart->irqn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0)); + EnableIRQ(uart->irqn); + + LOG_D("%s dma rx config done\n", uart->name); + } + + static void imxrt_dma_tx_config(struct imxrt_uart *uart) + { + RT_ASSERT(uart != RT_NULL); + + #ifndef SOC_IMXRT1180_SERIES + DMAMUX_SetSource(DMAMUX, uart->dma_tx->channel, uart->dma_tx->request); + DMAMUX_EnableChannel(DMAMUX, uart->dma_tx->channel); + #else + /* RT1180 uses EDMA4, configure DMA request source differently */ + EDMA_SetChannelMux(DMA0, uart->dma_tx->channel, uart->dma_tx->request); + #endif + + EDMA_CreateHandle(&uart->dma_tx->edma, DMA0, uart->dma_tx->channel); + + LPUART_TransferCreateHandleEDMA(uart->uart_base, + &uart->dma_tx->uart_edma, + edma_tx_callback, + uart, + &uart->dma_tx->edma, + RT_NULL); + + LOG_D("%s dma tx config done\n", uart->name); + } +#endif + uint32_t GetUartSrcFreq(LPUART_Type *uart_base) + { + uint32_t freq; + #if defined(SOC_IMXRT1170_SERIES) + uint32_t base = (uint32_t) uart_base; + switch (base) + { + case LPUART1_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1); + break; + case LPUART12_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart12); + break; + default: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart2); + break; + } + #elif defined(SOC_IMXRT1180_SERIES) + /* RT1180 uses different clock root architecture */ + uint32_t base = (uint32_t) uart_base; + switch (base) + { + case LPUART1_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); + break; + case LPUART2_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); + break; + case LPUART3_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304); + break; + case LPUART4_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0304); + break; + case LPUART5_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506); + break; + case LPUART6_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0506); + break; + case LPUART7_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708); + break; + case LPUART8_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0708); + break; + case LPUART9_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910); + break; + case LPUART10_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0910); + break; + case LPUART11_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112); + break; + case LPUART12_BASE: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1112); + break; + + default: + freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart0102); + break; + } + #else + /* To make it simple, we assume default PLL and divider settings, and the only variable from application is use PLL3 source or OSC source */ - if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ - { - freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - else - { - freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } -#endif - return freq; - -} - + if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ + { + freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + else + { + freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + #endif + return freq; + + } static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { struct imxrt_uart *uart;